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MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 1 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. features n video decoder ? supports ntsc, pal and secam video input formats ? 2d ntsc and pal comb-filter for y/c separation of cvbs input ? multiple cvbs and s-video inputs ? acc, agc, and dcgc (digital chroma gain control) n analog input ? supports rgb input format from pc, camcorders and gps ? supports ycbcr inputs from conventional video source and hdtv ? supports video input 480i, 480p, 576i, 576p, 720p, 1080i; 1080p; rgb input resolution in 640x480, 800x480, and 800x600, 1024x768, 1280x1024 ? 3-channel low-power 10-bit adcs integration for ycbcr and rgb ? supports rgb composite sync input (csync), soy, sog, hsync, and vsync ? on-chip clock synthesizer and pll ? auto-position adjustment, auto-phase adjustment, auto-gain adjustment, and auto-mode detection n color engine ? brightness, contrast, saturation, and hue adjustment ? 9-tap programmable multi-purpose fir (finite impulse response) filter ? differential 3-band peaking engine ? luminance transient improvement (lti) ? chrominance transient improvement (cti) ? black level extension (ble) ? white level extension (wle) ? favor color compensation (fcc) ? 3-channel gamma curve adjustment n scaling engine/panel interface ? supports lvds panel up to 1366x768 ? supports ttl/tcon and analog tcon panel ? supports single 8-bit ttl panel output ? supports various displaying modes ? supports horizontal panorama scaling n miscellaneous ? built-in mcu ? supports ccir656 digital input ? built-in internal osd with 256 programmable fonts, 16-color palettes, and 12-bit color resolution ? spread spectrum clocks ? 3.3v output pads with programmable driving current ? 100-pin lqfp package mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 2 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. block diagram switch 2-channel afe video decoder timing generator biu s-video 1/2 cvbs 1/2 yc separation 2d comb filter chroma demodulator t-con rgb /ycbcr mace mcu display device scaling engine osd gamma auto function for rgb / ycbcr adc input r/cr csc (rgb to ycbcr) 3x3 color space conversion display unit flash memory or eeprom external mcu g/y b/cb sy/cvbs sc m u x system application diagram deinterlacer / scaler video decoder tv / cable signal to digital panel flash / rom additional cvbs micro- controller tcon pwm step-down tv tuner dvd / vcd s-video signal additional s-video 1.8v ttl ttl out additional rgb signal hdtv ypbpr signal mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 3 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. general description the MST705 is a high quality asic for ntsc/pal/secam car tv application. it receives analog ntsc/pal/secam cvbs and s-video inputs from tv tuners, dvd or vcr sources, including weak and distorted signals, as well as analog ycbcr input from hdtv/sdtv systems. automatic gain control (agc) and 10-bit 3-channel a/d converters provide high resolution video quantization. with automatic video source and mode detection, users can easily switch and adjust variety of signal sources. multiple internal adaptive plls precisely extract pixel clock from video source and perform sharp color demodulation. built-in line-buffer supports adaptive 2-d comb-filter, 2-d sharpening, and synchronization stabler in a condense manner. the output format of MST705 supports 6-bit ttl/tcon and lvds digital tft-lcd modules. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 4 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. pin diagram (MST705) pin 1 1 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 36 37 38 39 40 67 66 65 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 64 81 80 79 78 77 76 75 74 73 72 71 70 69 68 100 99 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 clkin re set clko dac_vr p wm1d csn rxd_scl gnd vddp gnd r out[0]/lva3p hsynco/tcon[8] vddc rout[1]/lva3m vsynco/tcon[9] pwm2d gnd dac_vg de o/tcon[10] 96 h syncin sog0 cp_n avdd_ana rgbinm1 gin1/yin1 sog1 rin1/prin1 vcom0 cp_p rgbinm0 gin0/yin0 rin0/prin0 vsyncin agnd cvbs2/sy0 cvbs4/sy1 cvbs3/sc1 cvbs1/sc0 vddp dpwm_qor dpwm_ifb gnd vd[3] vd[2] vd[6] vd[5] vd[4] vd[0] vd[1] vd[7] sar1 gnd gnd sar0 vddc sar2 sck sdi sdo r out[5]/lva2m rout[6]/tcon[7] rout[4]/lva2p rout[3]/lvackm rout[2]/lvackp rout[7]/tcon[6] gout[1]/lva1m gout[2]/lva0p gout[3]/lva0m gout[0]/lva1p gout[4] gout[7]/tcon[4] gout[6]/tcon[5] gout[5] tcon[1] dac_vb gnd bout[7]/tcon[2] gpio[24]/pwm3d gpio[25]/pwm4d gpioe gpiod agnd xtal_out xtal_in bout[4] bout[3] bout[2] bout[5] bout[6]/tcon[3] avdd_mpll b in0/pbin0 gpioa txd_sda int vrep_dac vcomout avdd_dac bout[0] bout[1] b in1/pbin1 mst 705-lf xxxxxxxx xxx xxxxx mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 5 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. pin description analog panel output interface pin name pin type function pin dac_v r analog output red channel output 3.0 vp-p 76 dac_vg analog output green channel output 3.0 vp-p 77 dac_v b analog output blue channel output 3.0 vp-p 79 vrep_ dac analog input dac top reference voltage decoupling cap. 1uf to ground 80 vcomout analog output pulse output for common voltage. 81 analog interface pin name pin type function pin bin0/pbin0 analog input analog blue input from channel 0 2 sog0 analog input sync on green signal input from channel 0 3 gin0/yin0 analog input analog green input from channel 0 4 rgbinm0 analog input reference ground for analog green input from channel 0 5 rin0/prin0 analog input analog red input from channel 0 6 hsynci n schmitt trigger input w/ 5v-tolerant hsync / composite sync for vga input 7 vsynci n schmitt trigger input w/ 5v-tolerant vsync for vga input 8 bin1/pbin1 analog input analog blue input from channel 1 10 rgbinm1 analog input reference ground for analog green input from channel 1 11 gin1/yin1 analog input analog green input from channel 1 12 sog1 analog input sync on green signal input from channel 1 13 rin1/prin1 analog input analog red input from channel 1 14 vcom0 analog input common analog input reference ground 0 15 cvbs1/sc0 analog input cvbs0 or s-video (y/c) input channel 0 16 cvbs2/sy0 analog input cvbs1 or s-video (y/c) input channel 0 17 cvbs3/sc1 analog input cvbs2 or s-video (y/c) input channel 1 18 cvbs4/sy1 analog input cvbs3 or s-video (y/c) input channel 1 19 mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 6 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. switching power and pwm interface pin name pin type function pin cp_n output charge pump negative pulse for dc-dc positive voltage converter 24 cp_p output charge pump positive pulse for dc-dc positive voltage converter 25 internal mcu interface with serial flash memory pin name pin type function pin sar2 analog input sar low speed adc input 2 40 sar1 analog input sar low speed adc input 1 39 sar0 analog input sar low speed adc input 0 38 sck output spi interface sampling clock 41 sdi output spi interface data-in 42 sdo input w/ 5v-tolerant spi interface data-out 43 csn output spi interface chip select 44 int input interrupt input for ir receiver 46 txd_sda i/o w/ 5v-tolerant, w/ pull-up resistor serial bus data 47 rxd_scl input w/ 5v-tolerant serial bus clock 48 pwm2d output pulse width modulation output; 4ma driving strength 50 pwm1d output pulse width modulation output; 4ma driving strength 51 gpio[25]/pwm4d i/o w/ 5v-tolerant general purpose input/output / pulse width modulation output; 4ma driving strength 96 gpio[24]/pwm3d i/o w/ 5v-tolerant general purpose input/output / pulse width modulation output; 4ma driving strength 95 digital panel output interface pin name pin type function pin clko output display clock output 53 deo/tcon[10] output display enable output 54 vsynco/tcon[9] output vertical sync output / tcon output[9] 55 hsynco/tcon[8] output horizontal sync output / tcon output[8] 56 mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 7 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. pin name pin type function pin rout[7]/tcon[6] output red channel output [7] / tcon output[6] 67 rout[6]/tcon[7] output red channel output [6] / tcon output[7] 66 rout[5]/lva2 m output red channel output [5] / lvds a-link channel 2 negative data output 65 rout[4]/lva2 p output red channel output [4] / lvds a-link channel 2 positive data output 64 rout[3]/lvack m output red channel output [3] / lvds a-link negative clock output 63 rout[2]/lvack p output red channel output [2] / lvds a-link positive clock output 62 rout[1]/lva3 m output red channel output [1] / lvds a-link channel 3 negative data output 61 rout[0]/lva3 p output red channel output [0] / lvds a-link channel 3 positive data output 60 gout[7]/tcon[4] output green channel output [7] / tcon output[4] 75 gout[6]/tcon[5] output green channel output [6] / tcon output[5] 74 gout[5:4] output green channel output [5:4] 73, 72 gout[3]/lva0 m output green channel output [3] / lvds a-link channel 0 negative data output 71 gout[2]/lva0 p output green channel output [2] / lvds a-link channel 0 positive data output 70 gout[1]/lva1 m output green channel output [1] / lvds a-link channel 1 negative data output 69 gout[0]/lva1 p output green channel output [0] / lvds a-link channel 1 positive data output 68 bout[7]/tcon[2] output blue channel output [7] / tcon output[2] 90 bout[6]/tcon[3] output blue channel output [6] / tcon output[3] 89 bout[5:0] output blue channel output [5:0] 88-83 tcon[0] output tcon output[1] 92 digital video input interface pin name pin type function pin clkin input w/5v-tolerant sample clock itu656 video input 26 vd[7:0 ] input w/5v-toleran t itu656 video data bus 34-27 mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 8 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. switching power and pwm interface pin name pin type function pin cp_n output charge pump negative pulse for dc-dc positive voltage converter 24 cp_p output charge pump positive pulse for dc-dc positive voltage converter 25 gpio interface pin name pin type function pin gpioa i/o w/ 5v-tolerant general purpose input output; 4ma driving strength 45 gpiod i/o w/ 5v-tolerant general purpose input output; 4ma driving strength 93 gpioe i/o w/ 5v-tolerant general purpose input output; 4ma driving strength 94 digital pwm interface pin name pin type function pin dpwm_i fb analog input input for dpwm feedback loop 21 dpwm_ qor output dpwm output 22 misc. interface pin name pin type function pin reset schmitt trigger input w/ 5v-tolerant hardware reset; active high 52 xtal_in analog input crystal oscillator input 99 xtal_out analog output crystal oscillator output 98 power pins pin name pin type function pin avdd_ana 3.3v power analog adc power 1 avdd_dac 3.3v power voltage dac power 82 avdd_mpll 3.3v power mpll power 100 vddc 1.2v power digital core power 35, 57 vddp 3.3v power digital input/output power 23, 58 agnd ground analog ground 9, 97 gnd ground ground 20, 36, 37, 49, 59, 78, 91 mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 9 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. electrical specifications absolute maximum ratings parameter symbol min max units 3.3v supply voltages v vdd_33 3. 63 v 1.2v supply voltages v vdd_12 1. 32 v input voltage (5v tolerant inputs) v in5vtol 5. 0 v input voltage (non 5v tolerant inputs) v in v vdd_33 v ambient operating temperature t a 0 70 c storage temperature t stg - 40 125 c junction temperature t j 125 c note: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and does not imply functional operation of the device. exposure to absolute maximum ratings for extended periods may affect device reliability. ordering guide part number temperature range package description package option MST705-lf 0 c to +70 c lqfp 100 marking information MST705-lf operation code b date code (yyww) lot number operation code a part number disclaimer mstar semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. no responsibility is assumed by mstar semiconductor arising out of the application or user of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. revision history document description date MST705_ds_v01 ? initial release nov 2010 electrostatic charges accumulate on both test equipment and human body and can discharge without detection. MST705 comes with esd protection circuitry; however, the device may be permanently damaged when subjected to high energy discharges. the device should be handled with proper esd precautions to prevent malfunction and performance degradation. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 10 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mechanical dimensions e e 1 e 2 b l gauge plane 0.25mm e q seating plane d d1 d2 l1 a1 a2 a c millimeter inch symbol min. nom. max. min. nom. max. a - - 1.60 - - 0.063 a 1 0.05 - 0.15 0.002 - 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 d 16.00 bsc. 0.630 bsc. d1 14.00 bsc. 0.551 bsc. d 2 12.00 0.472 e 16.00 bsc. 0.630 bsc. e 1 14.00 bsc. 0.551 bsc. e2 12.00 0.472 millimeter inch symbol min. nom. max. min. nom. max. q 0 3.5 7 0 3.5 7 b 0.17 0.20 0.27 0.007 0.008 0.011 c 0.09 - 0.20 0.004 - 0.008 e 0.50 bsc. 0.020 bsc. l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 11 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. register description general control register general control register index name bits description regbk 7: 0 default : 0x00 access : r/w xtal_ok (ro) 7 crystal ready. mcu_sel (ro) 6 0 : embedded mcu. 1: external serial bus interface. - 5:4 reserved. ainc 3 se rial bus address auto increase. 0: enable. 1: disable. - 2 reserved. regbk[1:0] 1:0 register bank select. 00: register of scaler. 01: register of adc/ace/mcu. 10: register of video decoder front end (vfe). 11: register of video decoder 2d comb filter (vcf). 00h regbk[2:0] 2:0 register bank select. 000: register of scaler. 001: register of adc/ace/mcu. 010: register of video decoder front end (vfe). 011: register of video decoder 2d comb filter (vcf). 100: register of lvds/dpwm. - 7: 0 default : - access : - 01h ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 12 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank = 00, registers 01h ~ 9fh) scaler register (bank=00, registers 01h ~ 9fh) index name bits description dbfc 7: 0 default : 0x80 access : r/w - 7:3 reserved. dbl[1:0] 2:1 double buffer load. 00: keep old register value. 01: load new data (auto reset to 00 when load finish). 10: automatically load data at vsync blanking. 11: reserved. 01h db_en 0 double buffer enable. 0: disable. 1: enable. iselect 7: 0 default : 0x00 access : r/w nis 7 n o input source. 0: input source active. 1: input source inactive, output is free-run. stype[1:0] 6:5 input sync type. 00: auto detected. 01: input is separated hsync and vsync. 10: input is composite sync. 11: input is sync-on-green (sog). comp 4 csync/sog select (only useful when stype = 00). 0: csync. 1: sog. ics 3 input color space. 0: rgb. 1: ycbcr. ihsu 2 input sync usage. when extvd=0: 0: use hsync to perform mode detection, hsout from adc to sample pixel. 1: use hsync only. when extvd=1: 0: normal. 1: output black at blanking. bypassmd 1 by-pass mode for interlace-input-interlace-output. 02h extvd 0 0 : select analog input (cvbs/s-video/rgb/ycbcr). 1: select digital input (ccir656). 03h ipctrl2 7: 0 default : 0x18 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 13 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description vds_en 7 input data double sample in ccir input mode, 0: for horizontal output resolution less than 720 pixels. 1: for horizontal output resolution more than 720 pixels. in analog input mode, 0: half sample of input data. 1: original sample of input data. vds_mthd 6 input data double sample method. 0: using average. 1: using advance gt filter. ivds 5 input vsync delay select. 0: delay 1/4 input hsync (recommended). 1: no delay. hes 4 input hsync reference edge select. 0: from hsync leading edge, default value. 1: from hsync tailing edge. ves 3 input vsync reference edge select. 0: from vsync leading edge, default value. 1: from vsync tailing edge. esls 2 early sample line select. 0: 8 lines. 1: 16 lines. vwrp 1 input image vertical wrap. 0: disable. 1: enable. hwrp 0 input image horizontal wrap. 0: disable. 1: enable. isctrl 7: 0 default : 0x10 access : r/w dde 7 direct de mode for ccir input. 0: disable direct de. 1: enable direct de. degr[2:0] 6:4 de or hsync post glitch removal range. 04h hsfl 3 input hsync filter. 0: filter off. 1: filter on. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 14 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description issm 2 input sync sample mode. 0: normal. 1: glitch-removal. mvd_sel 1:0 mvd mode select 0: cvbs. 1: s-video. 2: ycbcr. 3: rgb. sprvst_l 7: 0 default : 0x10 access : r/w, db 05h sprvst[7:0] 7:0 image vertical sample start point, count by input hsync (lower 8 bits). sprvst_h 7: 0 default : 0x00 access : r/w, db - 7:3 reserved. 06h sprvst[10:8] 2:0 image vertical sample start point, count by input hsync (higher 3 bits). sprhst_l 7: 0 default : 0x01 access : r/w, db 07h sprhst[7:0] 7:0 image horizontal sample start point, count by input dot clock (higher 8 bits). sprhst_h 7: 0 default : 0x00 access : r/w, db - 7:3 reserved. 08h sprgst[10:8] 2:0 image horizontal sample start point, count by input dot clock (lower 3 bits). sprvdc_l 7: 0 default : 0x10 access : r/w, db 09h sprvdc[7:0] 7:0 image vertical resolution (vertical display enable area count by line; lower 8 bits). sprvdc_h 7: 0 default: 0x00 access : r/w - 7:3 reserved. 0ah sprvdc[10:8] 2:0 image vertical resolution (vertical display enable area count by line; higher 3 bits). sprhdc_l 7: 0 default : 0x10 access : r/w 0bh sprhdc[7:0] 7:0 image horizontal resolution (horizontal display enable area count by pixel; lower 8 bits). sprhdc_l 7: 0 default : 0x00 access : r/w - 7:3 reserved. 0ch sprhdc[10:8] 2:0 image horizontal resolution (horizontal display enable area count by pixel; higher 3 bits). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 15 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description lyl 7: 0 default : 0x00 access : r/w - 7:4 reserved. 0dh lyl[3:0] 3:0 lock y line. intlx 7: 0 default : 0x00 access : - itu_ext_field 7 us ing external field for itu interface. 0: using eav/sav. 1: using external field. itu_ext_hs 6 us ing external hsync for itu interface. 0: using eav/sav. 1: using external hsync. itu_ext_vs 5 us ing external vsync for itu interface. 0: using eav/sav. 1: using external vsync. vdoe 4 v ideo reference edge (for non-standard signal). intlac_locka vg 3 averaging locking timing. lhc_md 2 long horizontal counter mode. 1: on. 0: off. 0eh - 1:0 reserved. asctrl 7: 0 default : 0x90 access : r/w ivb (ro) 7 input vsync blanking status. 0: in display. 1: in blanking. dline[2:0] 6:4 line buffer read delay in number of lines. intlac_manstd 3 n tsc/pal manual mode intlac_setstd 2 n tsc/pal setting in manual mode under run status. 0: ntsc. 1: pal. under (ro) 1 u nder run status. 0fh over (ro) 0 over run status. coctrl1 7: 0 default : 0x00 access : r/w - 7:6 reserved. 10h avi_sel 5 analog video input select. 0: pc. 1: component analog video. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 16 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description dlyv 4 analog delay line for component analog video input. 0: delay 1 line. 1: do not delay. csc_md 3 composite sync cut mode. 0: disable. 1: enable. exvs 2 external vsync polarity (only used when covs is 1). 0: normal. 1: invert. cov_sel 1 coast vsync select. 0: internal vsep. 1: external vsync. cadc 0 coast to adc. 0: disable. 1: enable. coctrl2 7: 0 default : 0x00 access : r/w 11h cost[7:0] 7:0 front tuning. 00: coast start from 1 hsync leading edge. 01: coast start from 2 hsync leading edge, default value. 254: coast start from 255 hsync leading edge. 255: coast start from 256 hsync leading edge. coctrl3 7: 0 default : 0x00 access : r/w 12h coend[7:0] 7:0 end tuning. 00: coast end at 1 hsync leading edge. 01: coast end at 2 hsync leading edge, default value. 254: coast end at 255 hsync leading edge. 255: coast end at 256 hsync leading edge. vfac_oini 7: 0 default: 0x00 access : r/w 13h vfacoini[7:0] 7: 0 vertical factor odd initial value. vfac_eini 7: 0 default: 0x80 access : r/w 14h vfaceini[7:0] 7: 0 vertical factor even initial value - 7: 0 default : - access : - 15h - 7:0 reserved. 16h intctrol 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 17 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description chg_hmd 7 change h mode for int. 0: only in leading/tailing of chg period. 1: every line generating int pulse during chg period. - 6:4 reserved. ivsi 3 input vsync interrupt generated by: 0: leading edge. 1: tailing edge. ovsi 2 output vsync interrupt generated by: 0: leading edge. 1: tailing edge. trgc 1 trigger condition. 0: active low for level trigger/tailing edge trigger. 1: active high for level trigger/leading edge trigger. int_trig 0 interrupt trigger. 0: generate an edge trigger interrupt. 1: generate a level trigger interrupt. intpulse 7: 0 default : 0x0f access : r/w 17h intpulse[7:0] 7:0 interrupt pulse width by reference clock. intsta 7: 0 default : 0x00 access : r/w 18h intsta[7:0] 7:0 interrupt status byte a. bit 7: mvd input not no signal . bit 6: mvd hsync lock . bit 5: mvd not no color . bit 4: mvd degree error. bit 3: mvd input no signal . bit 2: mvd not hsync lock . bit 1: mvd no color . bit 0: mvd hsync change. intena 7: 0 default : 0x00 access : r/w 19h intena[7:0] 7:0 interrupt enable control byte a. 0: disable interrupt. 1: enable interrupt. 1ah intstb 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 18 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description intstb[7:0] 7:0 interrupt status byte b. bit 7: mcu d2b interrupt 2. bit 6: mcu d2b interrupt 1. bit 5: mcu d2b interrupt 0. bit 4: mvd cc interrupt. bit 3: mvd secam detect. bit 2: mvd pal switch error. bit 1: mvd adc7_0act . bit 0: mvd not adc7_0act . intenb 7: 0 default : 0x00 access : r/c 1bh intenb[7:0] 7:0 interrupt enable control byte b. 0: disable interrupt. 1: enable interrupt. intstc 7: 0 default : 0x00 access : r/w 1ch intstc[7:0] 7:0 interrupt status byte c. bit 7: output vsync interrupt. bit 6: input vsync interrupt. bit 5: atg ready interrupt. bit 4: atp ready interrupt. bit 3: ats ready interrupt. bit 2: mvd probe ready interrupt. bit 1: mcu d2b interrupt 4. bit 0: mcu d2b interrupt 3. intenc 7: 0 default : 0x00 access : r/c 1dh intenc[7:0] 7:0 interrupt enable control byte c. 0: disable interrupt. 1: enable interrupt. intstd 7: 0 default : 0x00 access : r/w 1eh intstd[7:0] 7:0 interrupt status byte d. bit 7: wdt interrupt. bit 6: keypad wake-up interrupt. bit 5: jitter interrupt. bit 4: horizontal total change interrupt. bit 3: vertical total change interrupt. bit 2: horizontal lost count interrupt. bit 1: vertical lost count interrupt. bit 0: standard change interrupt. 1fh intend 7: 0 default : 0x00 access : r/c mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 19 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description intend[7:0] 7:0 interrupt enable control byte d. 0: disable interrupt. 1: enable interrupt. - 7: 0 default : - access : - 20h ~ 21h - 7:0 reserved. mpl_m 7: 0 default : 0x6f access : r/w mp_ictrl[2:0] 7:5 charge pump current set. 22h mpl_m[4:0] 4:0 mpll divider ratio setting. opl_ctl0 7: 0 default : 0x40 access : r/w - 7:6 reserved. ssc_en 6 output pll spread spectrum. 0: disable. 1: enable. sd_md 5 output pll spread spectrum mode. 0: normal. 1: reverse for mode 1. 23h - 4:0 reserved. - 7: 0 default : - access : - 24h - 7:0 reserved. opl_set0 7: 0 default : 0x44 access : r/w, db 25h opl_set[7:0] 7:0 output pll set. opl_set1 7: 0 default : 0x55 access : r/w, db 26h opl_set[15:8] 7: 0 see description for opl_set [7:0]. opl_set2 7: 0 default : 0x24 access : r/w, db 27h opl_set [23:16] 7: 0 see description for opl_set [7:0]. opl_step0 7: 0 default : 0x20 access : r/w, db 28h opl_step[7:0] 7:0 output pll spread spectrum step. opl_step1 7: 0 default : 0x00 access : r/w, db - 7 reserved. - 6 reserved. - 5 reserved. - 4:3 reserved. 29h opl_step[10:8] 2: 0 see description for opl_step[7:0]. opl_span 7: 0 default : 0x00 access : r/w, db 2ah opl_span[7:0] 7:0 output pll spread spectrum span. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 20 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description opl_span 7: 0 default : 0x00 access : r/w, db read_frame 7 0 : opl_set stores line-based value. 1: opl_set stores frame-based value. 2bh opl_span[14:8] 6: 0 see description for opl_span[7:0]. - 7: 0 default : - access : - 2ch ~ 2fh - 7:0 reserved. hsr_l 7: 0 default : 0x00 access : r/w 30h hsr [7:0] 7: 0 horizontal scaling ratio (20 bits fraction) for scaling down 1/2^20 to (2^20-1)/2^20 (lower 8 bits). hsr_m 7: 0 default : 0x00 access : r/w 31h hsr[15:8] 7: 0 horizontal scaling ratio (20 bits fraction) for scaling down 1/2^20 to (2^20-1)/2^20 (middle 8 bits). hsr_h 7: 0 default : 0x00 access : r/w hs_en 7 h orizontal scaling enable. 0: disable. 1: enable. cbilinear_en 6 complemental bi-linear enable. forcebicolor 5 0 : chrominance using same setting as luminance defined by cbilinear. 1: chrominance always using bi-linear algorithm. - 4 reserved. 32h hsr[19:16] 3: 0 horizontal scaling ratio (20 bits fraction) for scaling down 1/2^20 to (2^20-1)/2^20 (higher 8 bits). vsr_l 7: 0 default : 0x00 access : r/w 33h vsr[7:0] 7: 0 vertical scaling ratio (2 bits integer, 20 bits fraction) for scaling down to 1/2.9999 (lower 8 bits). xx.xxxxxxxxxxxxxxxxxxxx vsr_m 7: 0 default : 0x00 access : r/w 34h vsr[15:8] 7: 0 vertical scaling ratio (2 bits integer, 20 bits fraction) for scaling down to 1/2.9999 (middle 8 bits). xx.xxxxxxxxxxxxxxxxxxxx vsr_h 7: 0 default : 0x00 access : r/w 35h vs_en 7 ve rtical scaling enable. 0: disable. 1: enable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 21 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description vsm_sel 6 ve rtical scaling method select. 0: original. 1: new. vsr[21:16] 5: 0 vertical scaling ratio (2 bits integer, 20 bits fraction) for scaling down to 1/2.9999 (higher 8 bits). xx.xxxxxxxxxxxxxxxxxxxx vdsusg 7: 0 default: 0x00 access : r/w lbf_inclk 7 line-buffer using input clock. lbf_outclk 6 line-buffer using output clock. lbf_live 5 line-buffer always live. outclk_div3 4 output clock is 1/3 frequency of opll output. en_ofst 3 enable offset for even/odd scaling. ofst_inv 2 offset inverting for even/odd scaling. lbfclk_div2 1 line-buffer clock frequency is divided by 2. 36h vsd_dith_en 0 vs d dither enable. dirscal_ctl 7: 0 default: 0x00 access : r/w - 7:3 reserved. goal2_sel 2 g oal2 select. dith_on 1 dithering control. 0: off. 1: on. 37h dirscal_en 0 function enable. nldti 7: 0 default : 0x00 access : r/w nl_en 7 n on-linear scaling enable. 38h nlsio[6:0] 6: 0 non-linear scaling section initial offset. nldt0 7: 0 default : 0x00 access : r/w nlios 7 n on-linear scaling section initial offset sign. 0: positive value. 1: negative value. 39h nldt0[6:0] 6: 0 non-linear scaling delta for section 0, bit 7 is sign bit. nldt1 7: 0 default : 0x00 access : r/w - 7 reserved 3ah nldt1[6:0] 6: 0 non-linear scaling delta for section 1, bit 7 is sign bit. nldc0 7: 0 default : 0x00 access : r/w 3bh nldc0[7:0] 7: 0 non-linear scaling section 0 dot count/2. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 22 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description nldc1 7: 0 default : 0x00 access : r/w 3ch nldc1[7:0] 7: 0 non-linear scaling section 1 dot count/2. nldc2 7: 0 default : 0x00 access : r/w 3dh nldc2[7:0] 7: 0 non-linear scaling section 2 dot count/2. dirscal_th 1 7: 0 default: 0x80 access : r/w 3eh detth[7:0] 7:0 threshold of maximum value for detection dirscal_th 2 7: 0 default: 0x80 access : r/w 3fh pctth[7:0] 7:0 threshold of maximum value for protection vfdest_l 7: 0 default : 0x01 access : r/w 40h vfdest[7:0] 7:0 output frame de vertical start (lower 8 bits). devst_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 41h vfdest[10:8] 2:0 output frame de vertical start (higher 3 bits). hfdest_l 7: 0 default : 0x03 access : r/w 42h hfdest[7:0] 7:0 output frame de horizontal start (lower 8 bits). hfdest_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 43h hfdest[10:8] 2:0 output frame de horizontal start (higher 3 bits). vfdeend_l 7: 0 default : 0xea access : r/w 44h vfdeend[7:0] 7:0 output frame de vertical end (lower 8 bits). vfdeend_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 45h devend[10:8] 2:0 output frame de vertical end (higher 3 bits). hfdeend_l 7: 0 default : 0xe0 access : r/w 46h hfdeend[7:0] 7:0 output frame de horizontal end (lower 8 bits). hfdeend_h 7: 0 default : 0x01 access : r/w - 7:3 reserved. 47h hfdeend[10:8] 2:0 output frame de horizontal end (higher 3 bits). sihst_l 7: 0 default : 0x01 access : r/w 48h sihst[7:0] 7: 0 scaling image window horizontal start (lower 8 bits). sihst_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 49h sihst[10:8] 2: 0 scaling image window horizontal start (higher 3 bits). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 23 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description sivend_l 7: 0 default : 0xea access : r/w 4ah sivend[7:0] 7: 0 scaling image window vertical end (lower 8 bits). sivend_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 4bh sivend[10:8] 2: 0 scaling image window vertical end (higher 3 bits). sihend_l 7: 0 default : 0xea access : r/w 4ch sihend[7:0] 7: 0 scaling image window horizontal end (lower 8 bits). sihend_h 7: 0 default : 0x01 access : r/w - 7:3 reserved. 4dh sihend[10:8] 2: 0 scaling image window horizontal end (higher 3 bits). vdtot_l 7: 0 default : 0x00 access : r/w 4eh vdtot[7:0] 7:0 output vertical total (lower 8 bits). vdtot_h 7: 0 default : 0x02 access : r/w - 7:3 reserved. 4fh vdtot[10:8] 2:0 output vertical total (higher 3 bits). vsst_l 7: 0 default : 0xea access : r/w 50h vsst[7:0] 7:0 output vsync start (lower 8 bits). vsst_h 7: 0 default : 0x00 access : r/w - 7:4 reserved. vsru 3 vsyn c register usage. 0: registers 20h C 23h are used to define output vsync. 1: registers 20h and 21h are used to define no signal vsync. registers 22h and 23h are used to define minimum h total. 51h vsst[10:8] 2:0 output vsync start (higher 3 bits). vsend_l 7: 0 default : 0x06 access : r/w 52h vsend[7:0] 7:0 output vsync end (lower 8 bits). vsend_h 7: 0 default : 0x00 access : r/w db - 7:3 reserved. 53h vsend[10:8] 2:0 output vsync end (higher 3 bits). hdtot_l 7: 0 default : 0x3c access : r/w db 54h hdtot[7:0] 7:0 output horizontal total (lower 8 bits). hdtot_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 55h hdtot[10:8] 2:0 output horizontal total (higher 3 bits). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 24 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description hsend 7: 0 default : 0x00 access : r/w 56h hsend[7:0] 7:0 output hsync end (lower 8 bits). osctrl1 7: 0 default : 0x4c access : r/w aovs 7 auto output vsync. 0: ovsync is defined automatically. 1: ovsync is defined manually (register 0x50 C 0x53). lcm 6 frame lock mode. 0: mode 0. 1: mode 1. hrsm 5 hs ync remove mode. 0: normal. 1: remove hsync. - 4:3 reserved. scal_1 2 s caling range add 1. ahrt 1 auto h total and read start tuning enable. 0: disable. 1: enable. 57h ctrl 0 atctrl function enable. 0: disable. 1: enable. brightness_en 7: 0 default : 0x00 access : r/w - 7:1 reserved. 58h bri_en 0 brightness function enable. 0: disable. 1: enable. bri_r 7:0 default : 0x80 access : r/w 59h bri_r[7:0] 7:0 brightness coefficient C red color. bri_g 7:0 default : 0x80 access : r/w 5ah bri_g[7:0] 7:0 brightness coefficient C green color. bri_b 7:0 default : 0x80 access : r/w 5bh bri_b[7:0] 7:0 brightness coefficient C blue color. frame_colo r_1 7: 0 default : 0x00 access : r/w fcg[4:3] 7:6 frame color g[4:3]. 5ch fcb[7:3] 5:1 frame color b[7:3]. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 25 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description fc_en 0 frame color enable. 0: diable. 1: enable. frame_colo r_2 7:0 default : 0x00 access : r/w fcr[7:3] 7:3 frame color r[7:3]. 5dh fcg[7:5] 2:0 frame color g[7:5]. pattern 7:0 default : 0x00 access : r/w ext_osd 7 ext osd pin as gpio. ext_vd 6 ext vd pin as gpio. - 5:3 reserved. ptnwt 2 pattern white. ptnblk 1 pattern black. 5eh ptnrvs 0 pattern reverse. ext_osd_ctrl 7:0 default : 0x00 access : r/w extosd_en 7 external osd function enable. 0: diable. 1: enable. datextmd[1:0] 6:5 data extend mode. ckey_en 4 color key enable. 0: disable. 1: enable. invckey_en 3 inverse color key enable. 0: diable. 1: enable. r_key 2 r color key selected. g_key 1 g color key selected. 5fh b_key 0 b color key selected. dithctrl 7: 0 default : 0x02 access : r/w dithg[1:0] 7:6 dither coefficient for g channel. dithb[1:0] 5:4 dither coefficient for b channel. srot 3 s patial coefficient rotate. 0: disable. 1: enable. 60h trot 2 temporal coefficient rotate. 0: disable. 1: enable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 26 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description obn 1 output bits number 0: 8-bit output. 1: 6-bit output (power on default value). dith 0 dither function. 0: off. 1: on. dithcoef 7:0 default : 0x2d access : r/w tl[1:0] 7:6 top-left dither coefficient. tr[1:0] 5:4 top-right dither coefficient. bl[1:0] 3:2 bottom-left dither coefficient. 61h br[1:0] 1:0 bottom-right dither coefficient. dithctl1 7:0 default : 0x00 access : r/w psrd 7 pseudo random, resets every 4 frames. 0: enable. 1: disable. nd_md 6 n oise dithering method. auto_dth 5 auto dither. psdo_en 4 pseudo enable. 0: disable. 1: enable. dth_mnus 3 dither minus. 62h abm[2:0] 2:0 alpha blending mode. 000: no alpha blending. 001: background alpha blending. 010: foreground alpha blending. 011: color key alpha blending. 100: not color key alpha blending. 101: entire osd alpha blending. 11x: reserved. 63h osd_ctl 7:0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 27 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description ckind[3:0] 7:4 color index of color key. 0000: color index 0. 0001: color index 1. 1111: color index 15. when osd register 0x10[7]=1, osd is not backward compatible. when osd register 0x10[7]=0, osd is backward compatible. when 8-color palette is selected, only ckind[2:0] are used. when 16-color palette is selected, osd0xe0 bit[6] is color key bit[3] instead of using ckind[3]. new_blnd_mthd 3 ne w blending level. 0: original blending level (blendl=000 means 0% transparency). 1: new blending level (blendl=000 means 12.5% transparency). osd_blnd_md 2:0 osd alpha blending level. 000: 12.5% transparency. 001: 25.0% transparency. 010: 37.5% transparency. 011: 50.0%% transparency. 100: 62.5% transparency. 101: 75.0% transparency. 110: 87.5% transparency. 111: 100% transparency. cm11_l 7:0 default : 0x00 access : r/w 64h cm11[7:0] 7:0 color matrix coefficient 11 (lower 8 bits). cm11_h 7:0 default : 0x04 access : r/w - 7:5 reserved. 65h cm11[12:8] 4:0 color matrix coefficient 11 (higher 5 bits). cm12_l 7:0 default : 0x00 access : r/w 66h cm12[7:0] 7:0 color matrix coefficient 12 (lower 8 bits). cm12_h 7:0 default : 0x00 access : r/w - 7:5 reserved. 67h cm12[12:8] 4:0 color matrix coefficient 12 (higher 5 bits). cm13_l 7:0 default : 0x00 access : r/w 68h cm13[7:0] 7:0 color matrix coefficient 13 (lower 8 bits). cm13_h 7:0 default : 0x00 access : r/w - 7:5 reserved. 69h cm13[12:8] 4:0 color matrix coefficient 13 (higher 5 bits). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 28 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description cm21_l 7:0 default : 0x00 access : r/w 6ah cm21[7:0] 7:0 color matrix coefficient 21 (lower 8 bits). cm21_h 7:0 default : 0x00 access : r/w - 7:5 reserved. 6bh cm21[12:8] 4:0 color matrix coefficient 21 (higher 5 bits). cm22_l 7:0 default : 0x00 access : r/w 6ch cm22[7:0] 7:0 color matrix coefficient 22 (lower 8 bits). cm22_h 7:0 default : 0x04 access : r/w - 7:5 reserved. 6dh cm22[12:8] 4:0 color matrix coefficient 22 (higher 5 bits). cm23_l 7:0 default : 0x00 access : r/w 6eh cm23[7:0] 7:0 color matrix coefficient 23 (lower 8 bits). cm23_h 7:0 default : 0x00 access : r/w - 7:5 reserved. 6fh cm23[12:8] 4:0 color matrix coefficient 23 (higher 5 bits). cm31_l 7:0 default : 0x00 access : r/w 70h cm31[7:0] 7:0 color matrix coefficient 31 (lower 8 bits). cm31_h 7:0 default : 0x00 access : r/w - 7:5 reserved. 71h cm31[12:8] 4:0 color matrix coefficient 31 (higher 5 bits). cm32_l 7:0 default : 0x00 access : r/w 72h cm32[7:0] 7:0 color matrix coefficient 32 (lower 8 bits). cm32_h 7:0 default : 0x00 access : r/w - 7:5 reserved. 73h cm32[12:8] 4:0 color matrix coefficient 32 (higher 5 bits). cm33_l 7:0 default : 0x00 access : r/w 74h cm33[7:0] 7:0 color matrix coefficient 33 (lower 8 bits). cm33_h 7:0 default : 0x04 access : r/w - 7:5 reserved. 75h cm33[12:8] 4:0 color matrix coefficient 33 (higher 5 bits). col_matrix_ctl 7: 0 default : 0x00 access : r/w 76h - 7:6 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 29 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description cmrnd 5 color matrix rounding control. 0: disable. 1: enable. cmc 4 color matrix control. 0: disable. 1: enable. - 3 reserved. rran 2 red range. 0: 0~255. 1: 128~127. gran 1 g reen range. 0: 0~255. 1: 128~127. bran 0 blue range. 0: 0~255. 1: 128~127. fbl_ctl 7: 0 default : 0x00 access : r/w - 7:5 reserved oddf 3 s hift odd field. 0: shift even field. 1: shift odd field. 77h sln[2:0] 2: 0 shift line number. 000: shift 0 line between odd and even fields. 001: shift 1 line between odd and even fields. 010: shift 2 line between odd and even fields. 011: shift 3 line between odd and even fields. 1xx: shift 4 line between odd and even fields. lck_vcnt_l 7: 0 default : - access : ro 78h lck_vcnt[7:0] 7:0 lock v total low byte [7:0]. lck_vcnt_h 7: 0 default : 0x00 access : r/w swch_sts 7 s witch status. - 6:3 reserved. 79h lck_vcnt[10:8] 2:0 lock v total high byte [10:8]. cap_vcnt_l 7: 0 default : - access : ro 7ah cap_vcnt[7:0] 7:0 cap v total low byte [7:0]. 7bh cap_vcnt_h 7: 0 default : - access : ro mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 30 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description - 7:3 reserved. cap_vcnt[10:8] 2:0 cap v total high byte [10:8]. cap_hcnt_l 7: 0 default : - access : ro 7ch cap_hcnt[7:0] 7:0 cap h total low byte [7:0]. cap_hcnt_h 7: 0 default : - access : ro - 7:3 reserved. 7dh cap_hcnt[10:8] 2:0 cap h total high byte [10:8]. est_vcnt_l 7: 0 default : - access : ro 7eh est_vcnt[7:0] 7:0 est v total low byte [7:0]. est_vcnt_h 7: 0 default : - access : ro - 7:3 reserved. 7fh est_vcnt[10:8] 2:0 est v total high byte [10:8]. est_hcnt_l 7: 0 default : 0x00 access : r/w 80h est_hcnt[7:0] 7:0 est h total low byte [7:0]. est_hcnt_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 81h est_hcnt[10:8] 2:0 est h total low byte [10:8]. ssc_tlrn 7: 0 default : 0x00 access : r/w 82h ssc_tlrn[7:0] 7: 0 ssc tolerance. delta_l 7: 0 default : 0x00 access : r/w 83h delta[7:0] 2:0 delta[7:0]. delta_h 7: 0 default : 0x00 access : r/w - 7:5 reserved. 84h delta[12:8] 4:0 delta[12:8]. ssc_shift 7: 0 default : 0x00 access : r/w 85h ssc_shift[7:0] 7: 0 ssc shift. fntn_tst 7: 0 default : 0x00 access : r/w - 7:6 reserved. msk_shrt_ln_cl k 5 mask the clock when in short line. - 4 reserved. sync_gate_md 3 mask hysnc and clock mode. rb_swap 2 output channel rb swap. 86h lm_swap_6 1 output channel msb lsb swap in 6-bit bus mode. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 31 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description lm_swap_8 0 output channel msb lsb swap in 8-bit bus mode. debug 7: 0 default : 0x00 access : r/w - 7 reserved. eock 6 se lect external odclk. - 5:4 reserved. pten 3 pll test register protect bit enable. 0: disable. 1: enable. 87h - 2:0 reserved. sl_cntrl_1 7: 0 default : 0x00 access : r/w - 7:6 reserved. lim_hs 5 limit hsync period enable. - 4:3 reserved. int_cap_en 2 interlace capture enable. shln_fld 1 se lect short line field. 88h frz_shln 0 s top short line update. sl_tune _1 7: 0 default : 0x70 access : r/w tncoef 7:5 tune coefficient. 89h lck_thrhd 4:0 lock threshold. sl_tune_2 7: 0 default : 0x00 access : r/w 8ah lmt_d5d6d7_ h 7:0 limit pll_set high byte. sl_tune_3 7: 0 default : 0xc0 access : r/w 8bh lmt_d5d6d7_l 7:0 limit pll_set low byte. target_sl_l 7: 0 default : 0x00 access : r/w 8ch target_sl_l 7:0 target short line low byte. target_sl_h 7: 0 default : 0x01 access : r/w 8dh target_sl_h 7:0 target short line high byte. - 7: 0 default : - access : ro 8eh ~ 8fh - reserved. gamma_en 7: 0 default : 0x00 access : r/w - 7:2 reserved. 90h adr_inc_en 1 address increase enable. 0: disable. 1: enable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 32 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers 01h ~ 9fh) index name bits description gamma_en 0 g amma enable. 0: disable. 1: enable. gamma_adr_port 7: 0 default : 0x00 access : r/w 91h gma_adr_port[7:0] 7: 0 gamma address port [7:0]. gamma_dat_port 7: 0 default : 0x00 access : r/w 92h gma_dat_port[7:0] 7: 0 gamma data port [7:0]. r_bias 7: 0 default : 0x00 access : r/w 93h r_bias[7:0] 7:0 dc level in r channel positive part. r_ratio 7: 0 default : 0x00 access : r/w 94h r_ratio[7:0] 7:0 ratio in r channel positive part. g_bias 7: 0 default : 0x00 access : r/w 95h g_bias[7:0] 7:0 dc level in g channel positive part. g_ratio 7: 0 default : 0x00 access : r/w 96h g_ratio[7:0] 7:0 ratio in g channel positive part. b_bias 7: 0 default : 0x00 access : r/w 97h b_bias[7:0] 7:0 dc level in b channel positive part. b_ratio 7: 0 default : 0x00 access : r/w 98h b_ratio[7:0] 7:0 ratio in b channel positive part. r_biasn 7: 0 default : 0x00 access : r/w 99h r_biasn[7:0] 7:0 dc level in r channel negative part. r_ration 7: 0 default : 0x00 access : r/w 9ah r_ration[7:0] 7:0 ratio in r channel negative part. g_biasn 7: 0 default : 0x00 access : r/w 9bh g_biasn[7:0] 7:0 dc level in g channel negative part. g_ration 7: 0 default : 0x00 access : r/w 9ch g_ration[7:0] 7:0 ratio in g channel negative part. b_biasn 7: 0 default : 0x00 access : r/w 9dh b_biasn[7:0] 7:0 dc level in b channel negative part. b_ration 7: 0 default : 0x00 access : r/w 9eh b_ration[7:0] 7:0 ratio in b channel negative part. - 7: 0 default : 0x00 access : r/w 9fh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 33 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (bank = 00, registers a0h ~ aah) osd register (bank=00) index mnemonic bits description osdioa 7: 0 default : 0x00 access : r/w tosb_md 7 osd sram i/o access burst mode. 0: disable. 1: enable. clr 6 osd clear bit (write only). 0: normal. 1: clear code with 00h, attribute with 00h. - 5 reserved. rf 4 osd ram font i/o access. 0: disable. 1: enable. dc 3 osd display code i/o access. 0: disable. 1: enable. da 2 osd display attribute i/o access. 0: disable. 1: enable. orbw_md 1 osd register burst write mode. 0: disable. 1: enable. a0h orbr_md 0 osd register burst read mode. 0: disable. 1: enable. osdra 7: 0 default : 0x00 access : r/w - 7:6 reserved. a1h osdra 5:0 osd register address port. osdrd 7: 0 default : 0x00 access : r/w a2h osdrd 7:0 osd register data port. osdfa 7: 0 default : - access : wo a3h osdfa 7:0 osd ram font address port. osdfd 7: 0 default : - access : wo a4h osdfd 7:0 osd ram font data port. dispca_l 7: 0 default : - access : wo a5h dispca[7:0] 7:0 osd display code address port. a6h dispca_h 7: 0 default : - access : wo mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 34 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (bank=00) index mnemonic bits description - 7:3 reserved. dispca[10:8] 2:0 osd display code address port. dispcd 7: 0 default : 0x00 access : r/w a7h dispcd[7:0] 7:0 osd display code data port (when write access disabled, this port report display code data). dispaa_l 7: 0 default : - access : wo a8h dispaa[7:0] 7:0 osd display attribute address port. dispaa_h 7: 0 default : - access : wo - 7:3 reserved. a9h dispaa[10:8] 2:0 osd display attribute address port. dispad 7: 0 default : 0x00 access : r/w aah dispad[7:0] 7:0 osd display attribute data port (when write access disabled, this port report display attribute data). dispca_ctl 7: 0 default : 0x00 access : r/w - 7 reserved. dispad_re[8] 6 when write access disabled, this bit report display attribute data (bit 8). - 5 reserved. dispcd_re[8] 4 when write access disabled, this bit report display code data (bit 8). - 3 reserved. ins_data 2 osd code/attribute 9th bit data (code (a7h)/attribute (aah) data extend bit). - 1 reserved. aeh ca_no_write 0 osd display code and attribute write disable. osd code (9th bit) italic 8 osd italic control 0: disable. 1: enable. (please refer aeh bit 0 ins_data) osd attribute (8-color palette) half_tran 8 osd half-transparency control. 0: disable. 1: enable. (please refer aeh[0]: ins_data and 42h[2]: alf_tranen) mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 35 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (bank=00) index mnemonic bits description blnk_ctrl 7 osd blink control. 0: disable. 1: enable. fgclr[2:0] 6:4 osd foreground color select. 000: color index 0. 001: color index 1. 111: color index 7. bder_ctrl 3 osd character border control. 0: disable. 1: enable. (please refer 42h[5] underline_md) bgclr[2:0] 2:0 osd background color select. 000: color index 0. 001: color index 1. 111: color index 7. osd attribute ( 16 color palette) fgclr[3:0] 7:4 osd foreground color select. 0000: color index 0. 0001: color index 1. 1111: color index 15. bgclr[3:0] 3:0 osd background color select. 0000: color index 0. 0001: color index 1. 1111: color index 15. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 36 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description osddbc 7: 0 default : 0x00 access : r/w - 7:3 reserved. dbl[1:0] 2:1 double buffer load. 00: keep old register value. 01: load new data (auto reset to 00 when loading completes). 10: automatically load data at vsync blanking. 11: reserved. 01h db_en 0 double buffer enable. 0: disable. 1: enable. ohsta-l 7: 0 default : 0x00 access : r/w 02h ohsta[7:0] 7:0 osd windows horizontal start position (pixel) (lower 8 bits). ohsta-h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 03h ohsta[10:8] 2:0 osd windows horizontal start position (higher 3 bits). ovsta-l 7: 0 default : 0x00 access : r/w 04h ovsta[7:0] 7:0 osd windows vertical start position (line) (lower 8 bits). ovsta-h 7: 0 default : 0x00 access : r/w - 7:2 reserved. 05h ovsta[9:8] 1:0 osd windows vertical start position (higher 2 bits). osdw 7: 0 default : 0x00 access : r/w - 7:6 reserved. 06h osdw[5:0] 5:0 osd windows width (osdw + 1 (column)), maximum 64 columns. osdh 7: 0 default : 0x00 access : r/w - 7:6 reserved. 07h osdh[5:0] 5:0 osd windows height (osdh + 1 (row)), maximum 64 rows. ohspa 7: 0 default : 0x00 access : r/w - 7:6 reserved. 08h ohspa[5:0] 5:0 osd windows horizontal space start position (ohspa + 1 (column)). ovspa 7: 0 default : 0x00 access : r/w - 7:5 reserved. 09h ovspa[4:0] 4:0 osd windows vertical space start position (ovspa + 1 (row)). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 37 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description ospw 7: 0 default : 0x00 access : r/w 0ah ospw[7:0] 7:0 osd space width (8 * ospw (pixel)). osph 7: 0 default : 0x00 access : r/w 0bh osph[7:0] 7:0 osd space height (8 * osph (line)). iosdc1 7: 0 default : 0x00 access : r/w ovs[1:0] 7:6 osd vertical scaling. 00: vertical normal size. 01: vertical enlarged x2 by repeated pixels. 10: vertical enlarged x3 by repeated pixels. 11: vertical enlarged x4 by repeated pixels. ohs[1:0] 5:4 osd horizontal scaling. 00: horizontal normal size. 01: horizontal enlarged x2 by repeated pixels. 10: horizontal enlarged x3 by repeated pixels. 11: horizontal enlarged x4 by repeated pixels. - 3:1 reserved. 0ch mwin 0 osd main window display. 0: off. 1: on. iosdc2 7: 0 default : 0x 00 access : r/w - 7:6 reserved. bdc 5 osd character border type select. 0: all direction font boundary (border). 1: bottom-right direction font boundary (shadow). bdw 4 osd character border width control. 0: one pixel with for all scale. 1: scale with ovs[1:0] and ohs[1:0]. - 3 reserved. 0dh bclr[2:0] 2:0 osd border color index. 000: color index 0. 001: color index 1. 111: color index 7. iosdc3 7: 0 default : 0x00 access : r/w 0eh - 7:6 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 38 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description shall 5 osd shadow with all direction. 0: shadow with bottom-right direction (shadow). 1: shadow with all direction (border). sdc 4 osd window shadow control. 0: off. 1: on. sclr[3:0] 3:0 osd window shadow color index. 0000: color index 0. 0001: color index 1. 1111: color index 15. oshc 7: 0 default : 0x00 access : r/w osdsh[3:0] 7:4 osd shadow height. 0fh osdsw[3:0] 3:0 osd shadow width. iosdc4 7: 0 default : 0x00 access : r/w line_shift_en 7 osd line shift enable (please refer 45h bit 4~2 line_shift_val). field_pol 6 osd line shift field polarity. - 5 reserved. en_m4c 4 4 color font enable. 0: disable. 1: enable. f16h 3 osd font high control. 0: font height is 18. 1: font height is 16. pext 2 osd 16 color palette extent method. 0: extend with palette bit 3. 1: extend with 0. tranen 1 osd transparency enable. 0: no transparency. 1: color index which hit osd color index for transparency[2:0] is transparent of 8 color palette/ color index which hit osd color index for transparency[3:0] is transparent of 16 color palette. (please refer 42h bit 3~0 osd color index for transparency.) 10h t16c 0 osd 16 color palette select. 0: 8 color palette. 1: 16 color palette. 12 h ocbufo 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 39 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description co_sel 7 osd code buffer offset select. 0: use osdw[5:0] as offset. 1: use ooffset[5:0] as offset. - 6 reserved. ooffset[5:0] 5:0 osd code buffer offset value. osdba-l 7: 0 default : 0x00 access : r/w 13h osdba[7:0] 7:0 osd code base address (lower 8 bits). osdba-h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 14h osdba[10:8] 2:0 osd code base address (higher 3 bits) (please refer 45h bit7 ccram608x2. when ccram608x2 = 0, osdba[10:0] is programming from 0 to 4bfh; when ccram608x2 = 1, osdba[9:0] is programming from 0 to 25fh and osdba[10] is programming to select low or high part code/attribute sram). gcctrl 7: 0 default : 0x00 access : r/w gvs[1:0] 7: 6 gradually color vertical scaling. 00: vertical normal size. 01: vertical enlarged x2 by repeated pixels. 10: vertical enlarged x3 by repeated pixels. 11: vertical enlarged x4 by repeated pixels. ghs[1:0] 5: 4 gradually color horizontal scaling. 00: horizontal normal size. 01: horizontal enlarged x2 by repeated pixels. 10: horizontal enlarged x3 by repeated pixels. 11: horizontal enlarged x4 by repeated pixels. grad 3 enable osd gradual color function. 0: disable. 1: enable. adc_pg 2 adc pattern generator select. 0: normal. 1: adc. 15h svm_sel 1: 0 svm mask signal select. 00: original active signal. 01: 2t early. 10: 4t early. 11: 6t early. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 40 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description gradclr 7: 0 default : 0x00 access : r/w fclr 7 g radual color by frame color. 0: use rclr, gclr, bclr as starting gradual color. 1: use frame color as starting gradual color. - 6 reserved. rclr[1:0] 5:4 red starting gradual color. 00: red color is 00h. 01: red color is 55h. 10: red color is aah. 11: red color is ffh. gclr[1:0] 3: 2 green starting gradual color. 00: green color is 00h. 01: green color is 55h. 10: green color is aah. 11: green color is ffh. 16h bclr[1:0] 1:0 blue starting gradual color. 00: blue color is 00h. 01: blue color is 55h. 10: blue color is aah. 11: blue color is ffh. hgradcr 7: 0 default : 0x00 access : r/w sr 7 s ign bit of red color. 0: increase. 1: decrease. irh 6 inverse bit of red color. 0: normal. 1: invert. 17h r_gradh[5:0] 5:0 increase/decrease value of red color. hgradcg 7: 0 default : 0x00 access : r/w sg 7 s ign bit of green color. 0: increase. 1: decrease. igh 6 inverse bit of green color. 0: normal. 1: invert. 18h g_gradh[5:0] 5:0 increase/decrease value of green color. 19h hgradcb 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 41 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description sb 7 s ign bit of blue color. 0: increase. 1: decrease. ibh 6 inverse bit of blue color. 0: normal. 1: invert. b_gradh[5:0] 5:0 increase/decrease value of blue color. hgradsr 7: 0 default : 0x00 access : r/w 1ah hgradsr[7:0] 7: 0 horizontal gradual step of red color. hgradsg 7: 0 default : 0x00 access : r/w 1bh hgradsg[7:0] 7: 0 horizontal gradual step of green color. hgradsb 7: 0 default : 0x00 access : r/w 1ch hgradsb[7:0] 7: 0 horizontal gradual step of blue color. vgradcr 7: 0 default : 0x00 access : r/w sr 7 s ign bit of red color. 0: increase. 1: decrease. irv 6 inverse bit of red color. 0: normal. 1: invert. 1dh r_gradv[5:0] 5:0 increase/decrease value of red color. vgradcg 7: 0 default : 0x00 access : r/w sg 7 s ign bit of green color. 0: increase. 1: decrease. igv 6 inverse bit of green color. 0: normal. 1: invert. 1eh g_gradv[5:0] 5:0 increase/decrease value of green color. vgradcb 7: 0 default : 0x00 access : r/w sb 7 s ign bit of blue color. 0: increase. 1: decrease. 1fh ibv 6 inverse bit of blue color. 0: normal. 1: invert. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 42 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description b_gradv[5:0] 5:0 increase/decrease value of blue color. vgradsr 7: 0 default : 0x00 access : r/w 20h vgradsr[7:0] 7: 0 vertical gradual step of red color. vgradsg 7: 0 default : 0x00 access : r/w 21h vgradsg[7:0] 7: 0 vertical gradual step of green color. vgradsb 7: 0 default : 0x00 access : r/w 22h vgradsb[7:0] 7: 0 vertical gradual step of blue color. - 7: 0 default : - access : - 23h ~ 25h - 7:0 reserved. timectrl 7: 0 default : 0x00 access : r/w - 7:5 reserved. frg_en 4 osd font ram gated enable. 0: disable. 1: enable. - 3:2 reserved vstdly 1 osd vertical start delay. 0: normal. 1: vertical delay 1 line. 26h - 0 reserved. osdrtp 7: 0 default : 0x00 access : r/w - 7:3 reserved. rtpt 2 osd random test pattern type. 0: rgb is the same. 1: rgb is different. 27h osdrtp[1:0] 1:0 osd random test pattern. 00: disable. 01: 1 random bit. 10: 2 random bit. 11: reserved. osd color palette when t16_c = 0 clr0r 7: 0 default : 0x00 access : r/w 28h clr0r[7:0] 7:0 red color index 0. clr0g 7: 0 default : 0x00 access : r/w 29h clr0g[7:0] 7: 0 green color index 0. 2ah clr0b 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 43 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description clr0b[7:0] 7:0 blue color index 0. clr1r 7: 0 default : 0x00 access : r/w 2bh clr1r[7:0] 7:0 red color index 1. clr1g 7: 0 default : 0x00 access : r/w 2ch clr1g[7:0] 7: 0 green color index 1. clr1b 7: 0 default : 0x00 access : r/w 2dh clr1b[7:0] 7:0 blue color index 1. clr2r 7: 0 default : 0x00 access : r/w 2eh clr2r[7:0] 7:0 red color index 2. clr2g 7: 0 default : 0x00 access : r/w 2fh clr2g[7:0] 7: 0 green color index 2. clr2b 7: 0 default : 0x00 access : r/w 30h clr2b[7:0] 7:0 blue color index 2. clr3r 7: 0 default : 0x00 access : r/w 31h clr3r[7:0] 7:0 red color index 3. clr3g 7: 0 default : 0x00 access : r/w 32h clr3g[7:0] 7: 0 green color index 3. clr3b 7: 0 default : 0x00 access : r/w 33h clr3b[7:0] 7:0 blue color index 3. clr4r 7: 0 default : 0x00 access : r/w 34h clr4r[7:0] 7:0 red color index 4. clr4g 7: 0 default : 0x00 access : r/w 35h clr4g[7:0] 7: 0 green color index 4. clr4b 7: 0 default : 0x00 access : r/w 36h clr4b[7:0] 7:0 blue color index 4. clr5r 7: 0 default : 0x00 access : r/w 37h clr5r[7:0] 7:0 red color index 5. clr5g 7: 0 default : 0x00 access : r/w 38h clr5g[7:0] 7: 0 green color index 5. clr5b 7: 0 default : 0x00 access : r/w 39h clr5b[7:0] 7:0 blue color index 5. clr6r 7: 0 default : 0x00 access : r/w 3ah clr6r[7:0] 7:0 red color index 6. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 44 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description clr6g 7: 0 default : 0x00 access : r/w 3bh clr6g[7:0] 7: 0 green color index 6. clr6b 7: 0 default : 0x00 access : r/w 3ch clr6b[7:0] 7:0 blue color index 6. clr7r 7: 0 default : 0x00 access : r/w 3dh clr7r[7:0] 7:0 red color index 7. clr7g 7: 0 default : 0x00 access : r/w 3eh clr7g[7:0] 7: 0 green color index 7. clr7b 7: 0 default : 0x00 access : r/w 3fh clr7b[7:0] 7:0 blue color index 7. osd color palette when t16_c = 1 (16 color format: col[7:4], 4 b0 or col[7:4], {4{col[4]}}) clr0r 7: 0 default : 0x00 access : r/w clr0r[7:4] 7:4 red color index 0. 28h clr8r[3:0] 3:0 red color index 8. clr0g 7: 0 default : 0x00 access : r/w clr0g[7:4] 7: 4 green color index 0. 29h clr8g[3:0] 3: 0 green color index 8. clr0b 7: 0 default : 0x00 access : r/w clr0b[7:4] 7:4 blue color index 0. 2ah clr8b[3:0] 3:0 blue color index 8. clr1r 7: 0 default : 0x00 access : r/w clr1r[7:4] 7:4 red color index 1. 2bh clr9r[3:0] 3:0 red color index 9. clr1g 7: 0 default : 0x00 access : r/w clr1g[7:4] 7: 4 green color index 1. 2ch clr9g[3:0] 3: 0 green color index 9. clr1b 7: 0 default : 0x00 access : r/w clr1b[7:4] 7:4 blue color index 1. 2dh clr9b[3:0] 3:0 blue color index 9. clr2r 7: 0 default : 0x00 access : r/w clr2r[7:4] 7:4 red color index 2. 2eh clr10r[3:0] 3:0 red color index 10. 2fh clr2g 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 45 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description clr2g[7:4] 7: 4 green color index 2. clr10g[3:0] 3: 0 green color index 10. clr2b 7: 0 default : 0x00 access : r/w clr2b[7:4] 7:4 blue color index 2. 30h clr10b[3:0] 3:0 blue color index 10. clr3r 7: 0 default : 0x00 access : r/w clr3r[7:4] 7:4 red color index 3. 31h clr11r[3:0] 3:0 red color index 11. clr3g 7: 0 default : 0x00 access : r/w clr3g[7:4] 7: 4 green color index 3. 32h clr11g[3:0] 3: 0 green color index 11. clr3b 7: 0 default : 0x00 access : r/w clr3b[7:4] 7:4 blue color index 3. 33h clr11b[3:0] 3:0 blue color index 11. clr4r 7: 0 default : 0x00 access : r/w clr4r[7:4] 7:4 red color index 4. 34h clr12r[3:0] 3:0 red color index 12. clr4g 7: 0 default : 0x00 access : r/w clr4g[7:4] 7: 4 green color index 4. 35h clr12g[3:0] 3: 0 green color index 12. clr4b 7: 0 default : 0x00 access : r/w clr4b[7:4] 7:4 blue color index 4. 36h clr12b[3:0] 3:0 blue color index 12. clr5r 7: 0 default : 0x00 access : r/w clr5r[7:4] 7:4 red color index 5. 37h clr13r[3:0] 3:0 red color index 13. clr5g 7: 0 default : 0x00 access : r/w clr5g[7:4] 7: 4 green color index 5. 38h clr13g[3:0] 3: 0 green color index 13. clr5b 7: 0 default : 0x00 access : r/w clr5b[7:4] 7:4 blue color index 5. 39h clr13b[3:0] 3:0 blue color index 13. 3ah clr6r 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 46 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description clr6r[7:4] 7:4 red color index 6. clr14r[3:0] 3:0 red color index 14. clr6g 7: 0 default : 0x00 access : r/w clr6g[7:4] 7: 4 green color index 6. 3bh clr14g[3:0] 3: 0 green color index 14. clr6b 7: 0 default : 0x00 access : r/w clr6b[7:4] 7:4 blue color index 6. 3ch clr14b[3:0] 3:0 blue color index 14. clr7r 7: 0 default : 0x00 access : r/w clr7r[7:4] 7:4 red color index 7. 3dh clr15r[3:0] 3:0 red color index 15. clr7g 7: 0 default : 0x00 access : r/w clr7g[7:4] 7: 4 green color index 7. 3eh clr15g[3:0] 3: 0 green color index 15. clr7b 7: 0 default : 0x00 access : r/w clr7b[7:4] 7:4 blue color index 7. 3fh clr15b[3:0] 3:0 blue color index 15. scrlspd 7: 0 default : 0x00 access : r/w 40h scrlspd[7:0] 7:0 osd scroll function speed (the numbers of vsync). scrlline 7: 0 default : 0x00 access : r/w scren 7 osd scroll function enable. 0: disable. 1: enable. vscr_fast 6 s croll at every vsync. truc_en 5 truncate code/attribute enable. 0: disable. 1: enable. 41h scrlline[4:0] 4:0 osd scroll function (the numbers of scan lines per scroll). underline 7: 0 default : 0x0f access : r/w underline_1 7 osd underline at last line. underline_2 6 osd underline at second last line. 42h underline_md 5 osd underline mode enable (when this bit is asserted, osd attribute (8 color) bit 3. (bder) character boder control change function to osd character underline control). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 47 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description half_tranen 4 osd half-transparency enable (when this bit is asserted, osd attribute (8 color) bit 9 (half_tran) is active.). tran_index[3:0] 3:0 osd color index for transparency (define which color index is transparent). truncate 7: 0 default : 0x 1d access : r/w 43h truncatenum 7:0 osd truncate number (please refer 45h bit7 ccram608x2. when ccram608x2=0, final row=(11 h4bf-truncatenum); when ccram608x2=1, final row=(11 h25f-truncatenum)). italic 7: 0 default : 0x 00 access : r/w italic_offset 7:6 osd italic right shift offset (00: 1, 01: 2, 10: 3, 11: 4 (pixel)). italic_1st_line 5:4 osd italic start scan line (00: 0, 01: 1, 10: 2, 11: 3 (line)). italic_step 3:2 osd italic left shift step (00: 0.001, 01: 0.010, 10: 0.011, 11: 0.100 (pixel , binary)). italic_en 1 osd italic function enable. 0: disable. 1: enable. 44h - 0 reserved. misc_ctl 7: 0 default : 0x00 access : r/w ccram608x2 7 osd 2 608 code/attribute sram (when ccram608x2 = 0, there is one 1216 code/attribute sram for using; when ccram608x2 = 1, there are two 608 code/attribute sram for using.). - 6:5 reserved. line_shift_val[2:0] 4:2 osd line shift value (line shift number, 000: 1, , 111: 8). carhg_en 1 osd code/attribute high part ram gated enable. 0: disable. 1: enable. 45h - 0 reserved. osd4cffa 7: 0 default : 0x00 access : r/w 46h osd4cffa[7:0] 7:0 osd 4 color font ram start address (must be even number). - 7: 0 default : - access : - 47h ~ 49h - 7:0 reserved. ohvsta-h 7: 0 default : 0x00 access : ro vscr_opt 7 vs croll option. 0: original. 1: fixed. 4ah - 6 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 48 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description ovsta[9:8] 5:4 osd windows vertical start position (read only). - 3 reserved. ohsta[10:8] 2:0 osd windows horizontal start position. (read only). - 7: 0 default : - access : - 4bh ~ 4ch - 7:0 reserved. osdbri 7: 0 default : 0x00 access : r/w osdbri_en 7 osd brightness enable. 0: disable. 1: enable. osdbri_dir 6 osd brightness control. 0: add. 1: subtract. 4dh osdbri_val[5:0] 5:0 osd brightness value. - 7: 0 default : - access : - 4eh ~ 4fh - 7:0 reserved. codeclrdata_l 7: 0 default : 0x00 access : r/w 50h codeclrdata[7:0] 7:0 osd code clear data. atrclrdata_l 7: 0 default : 0x00 access : r/w 51h atrclrdat[7:0] 7:0 osd attribute clear data (lower 8 bits). osdclrdata 7: 0 default : 0x00 access : r/w - 7:5 reserved. atrclrdat[8] 4 osd attribute clear data. - 3:1 reserved. 52h codeclrdat[8] 0 osd code clear data. osdclradr_l 7: 0 default : 0x00 access : r/w 53h osdclr_adr[7:0] 7:0 osd clear starting address (lower 8 bits). osdclradr_h 7: 0 default : 0x00 access : r/w atr1_clren 7 osd attribute high clear enable. atr0_clren 6 osd attribute low clear enable. code1_clren 5 osd code high clear enable. code0_clren 4 osd code low clear enable. - 3:2 reserved. 54h osdclr_adr[9:8] 1:0 osd clear starting address. 55 h osdclr_ofst 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 49 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. osd register (indirect mapping to bank 00, registers a1h/a2) index mnemonic bits description - 7 reserved osdclr_ofst[6:0] 6:0 osd clear offset. osdclr_wi d 7: 0 default : 0x00 access : r/w - 7 reserved. 56h osdclr_wid[6:0] 6:0 osd clear width. osdclr_higt 7: 0 default : 0x00 access : r/w - 7 reserved. 57h osdclr_higt[6:0] 6:0 osd clear height. osdclr_ctrl 7: 0 default : 0x00 access : r/w - 7:1 reserved. 58h blk_clr_en 0 osd block clear enable. - 7: 0 default : - access : - 59h ~ 9fh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 50 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_r00 7: 0 default : 0d00 access : r/w 00h gamma_r00 7: 0 gamma_table r00 value. gamma_r01 7: 0 default : 0d07 access : r/w 01h gamma_r01 7: 0 gamma_table r01 value. gamma_r02 7: 0 default : 0d15 access : r/w 02h gamma_r02 7: 0 gamma_table r02 value. gamma_r03 7: 0 default : 0d23 access : r/w 03h gamma_r03 7: 0 gamma_table r03 value. gamma_r04 7: 0 default : 0d31 access : r/w 04h gamma_r04 7: 0 gamma_table r04 value. gamma_r05 7: 0 default : 0d39 access : r/w 05h gamma_r05 7: 0 gamma_table r05 value. gamma_r06 7: 0 default : 0d47 access : r/w 06h gamma_r06 7: 0 gamma_table r06 value. gamma_r07 7: 0 default : 0d55 access : r/w 07h gamma_r07 7: 0 gamma_table r07 value gamma_r08 7: 0 default : 0d63 access : r/w 08h gamma_r08 7: 0 gamma_table r08 value. gamma_r09 7: 0 default : 0d71 access : r/w 09h gamma_r09 7: 0 gamma_table r09 value. gamma_r10 7: 0 default : 0d79 access : r/w 0ah gamma_r10 7: 0 gamma_table r10 value. gamma_r11 7: 0 default : 0d87 access : r/w 0bh gamma_r11 7: 0 gamma_table r11 value. gamma_r12 7: 0 default : 0d95 access : r/w 0ch gamma_r12 7: 0 gamma_table r12 value. gamma_r13 7: 0 default : 0d103 access : r/w 0dh gamma_r13 7: 0 gamma_table r13 value. gamma_r14 7: 0 default : 0d111 access : r/w 0eh gamma_r14 7: 0 gamma_table r14 value. gamma_r15 7: 0 default : 0d119 access : r/w 0fh gamma_r15 7: 0 gamma_table r15 value. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 51 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_r16 7: 0 default : 0d127 access : r/w 10h gamma_r16 7: 0 gamma_table r16 value. gamma_r17 7: 0 default : 0d135 access : r/w 11h gamma_r17 7: 0 gamma_table r17 value. gamma_r18 7: 0 default : 0d143 access : r/w 12h gamma_r18 7: 0 gamma_table r18 value. gamma_r19 7: 0 default : 0d151 access : r/w 13h gamma_r49 7: 0 gamma_table r19 value. gamma_r20 7: 0 default : 0d159 access : r/w 14h gamma_r20 7: 0 gamma_table r20 value. gamma_r21 7: 0 default : 0d167 access : r/w 15h gamma_r21 7: 0 gamma_table r21 value. gamma_r22 7: 0 default : 0d175 access : r/w 16h gamma_r22 7: 0 gamma_table r22 value. gamma_r23 7: 0 default : 0d183 access : r/w 17h gamma_r23 7: 0 gamma_table r23 value. gamma_r24 7: 0 default : 0d191 access : r/w 18h gamma_r24 7: 0 gamma_table r24 value. gamma_r25 7: 0 default : 0d199 access : r/w 19h gamma_r25 7: 0 gamma_table r25 value. gamma_r26 7: 0 default : 0d207 access : r/w 1ah gamma_r26 7: 0 gamma_table r26 value. gamma_r27 7: 0 default : 0d215 access : r/w 1bh gamma_r27 7: 0 gamma_table r27 value. gamma_r28 7: 0 default : 0d223 access : r/w 1ch gamma_r28 7: 0 gamma_table r28 value. gamma_r29 7: 0 default : 0d232 access : r/w 1dh gamma_r29 7: 0 gamma_table r29 value. gamma_r30 7: 0 default : 0d239 access : r/w 1eh gamma_r30 7: 0 gamma_table r30 value. gamma_r31 7: 0 default : 0d247 access : r/w 1fh gamma_r31 7: 0 gamma_table r31 value. 20h gamma_r32 7: 0 default : 0d255 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 52 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_r32 7: 0 gamma_table r32 value. gamma_g00 7: 0 default : 0d00 access : r/w 21h gamma_g00 7: 0 gamma_table g00 value. gamma_g01 7: 0 default : 0d07 access : r/w 22h gamma_g01 7: 0 gamma_table g01 value. gamma_g02 7: 0 default : 0d15 access : r/w 23h gamma_g02 7: 0 gamma_table g02 value. gamma_g03 7: 0 default : 0d23 access : r/w 24h gamma_g03 7: 0 gamma_table g03 value. gamma_g04 7: 0 default : 0d31 access : r/w 25h gamma_g04 7: 0 gamma_table g04 value. gamma_g05 7: 0 default : 0d39 access : r/w 26h gamma_g05 7: 0 gamma_table g05 value. gamma_g06 7: 0 default : 0d47 access : r/w 27h gamma_g06 7: 0 gamma_table g06 value. gamma_g07 7: 0 default : 0d55 access : r/w 28h gamma_g07 7: 0 gamma_table g07 value. gamma_g08 7: 0 default : 0d63 access : r/w 29h gamma_g08 7: 0 gamma_table g08 value. gamma_g09 7: 0 default : 0d71 access : r/w 2ah gamma_g09 7: 0 gamma_table g09 value. gamma_g10 7: 0 default : 0d79 access : r/w 2bh gamma_g10 7: 0 gamma_table g10 value. gamma_g11 7: 0 default : 0d87 access : r/w 2ch gamma_g11 7: 0 gamma_table g11 value. gamma_g12 7: 0 default : 0d95 access : r/w 2dh gamma_g12 7: 0 gamma_table g12 value. gamma_g13 7: 0 default : 0d103 access : r/w 2eh gamma_g13 7: 0 gamma_table g13 value. gamma_g14 7: 0 default : 0d111 access : r/w 2fh gamma_g14 7: 0 gamma_table g14 value. gamma_g15 7: 0 default : 0d119 access : r/w 30h gamma_g15 7: 0 gamma_table g15 value. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 53 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_g16 7: 0 default : 0d127 access : r/w 31h gamma_g16 7: 0 gamma_table g16 value. gamma_g17 7: 0 default : 0d135 access : r/w 32h gamma_g17 7: 0 gamma_table g17 value. gamma_g18 7: 0 default : 0d143 access : r/w 33h gamma_g18 7: 0 gamma_table g18 value. gamma_g19 7: 0 default : 0d151 access : r/w 34h gamma_g49 7: 0 gamma_table g19 value. gamma_g20 7: 0 default : 0d159 access : r/w 35h gamma_g20 7: 0 gamma_table g20 value. gamma_g21 7: 0 default : 0d167 access : r/w 36h gamma_g21 7: 0 gamma_table g21 value. gamma_g22 7: 0 default : 0d175 access : r/w 37h gamma_g22 7: 0 gamma_table g22 value. gamma_g23 7: 0 default : 0d183 access : r/w 38h gamma_g23 7: 0 gamma_table g23 value. gamma_g24 7: 0 default : 0d191 access : r/w 39h gamma_g24 7: 0 gamma_table g24 value. gamma_g25 7: 0 default : 0d199 access : r/w 3ah gamma_g25 7: 0 gamma_table g25 value. gamma_g26 7: 0 default : 0d207 access : r/w 3bh gamma_g26 7: 0 gamma_table g26 value. gamma_g27 7: 0 default : 0d215 access : r/w 3ch gamma_g27 7: 0 gamma_table g27 value. gamma_g28 7: 0 default : 0d223 access : r/w 3dh gamma_g28 7: 0 gamma_table g28 value. gamma_g29 7: 0 default : 0d232 access : r/w 3eh gamma_g29 7: 0 gamma_table g29 value. gamma_g30 7: 0 default : 0d239 access : r/w 3fh gamma_g30 7: 0 gamma_table g30 value. gamma_g31 7: 0 default : 0d247 access : r/w 40h gamma_g31 7: 0 gamma_table g31 value. 41h gamma_g32 7: 0 default : 0d255 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 54 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_g32 7: 0 gamma_table g32 value. gamma_b00 7: 0 default : 0d00 access : r/w 42h gamma_b00 7: 0 gamma_table b00 value. gamma_b01 7: 0 default : 0d07 access : r/w 43h gamma_b01 7: 0 gamma_table b01 value. gamma_b02 7: 0 default : 0d15 access : r/w 44h gamma_b02 7: 0 gamma_table b02 value. gamma_b03 7: 0 default : 0d23 access : r/w 45h gamma_b03 7: 0 gamma_table b03 value. gamma_b04 7: 0 default : 0d31 access : r/w 46h gamma_b04 7: 0 gamma_table b04 value. gamma_b05 7: 0 default : 0d39 access : r/w 47h gamma_b05 7: 0 gamma_table b05 value. gamma_b06 7: 0 default : 0d47 access : r/w 48h gamma_b06 7: 0 gamma_table b06 value. gamma_b07 7: 0 default : 0d55 access : r/w 49h gamma_b07 7: 0 gamma_table b07 value. gamma_b08 7: 0 default : 0d63 access : r/w 4ah gamma_b08 7: 0 gamma_table b08 value. gamma_b09 7: 0 default : 0d71 access : r/w 4bh gamma_b09 7: 0 gamma_table b09 value. gamma_b10 7: 0 default : 0d79 access : r/w 4ch gamma_b10 7: 0 gamma_table b10 value. gamma_b11 7: 0 default : 0d87 access : r/w 4dh gamma_b11 7: 0 gamma_table b11 value. gamma_b12 7: 0 default : 0d95 access : r/w 4eh gamma_b12 7: 0 gamma_table b12 value. gamma_b13 7: 0 default : 0d103 access : r/w 4fh gamma_b13 7: 0 gamma_table b13 value. gamma_b14 7: 0 default : 0d111 access : r/w 50h gamma_b14 7: 0 gamma_table b14 value. gamma_b15 7: 0 default : 0d119 access : r/w 51h gamma_b15 7: 0 gamma_table b15 value. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 55 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_b16 7: 0 default : 0d127 access : r/w 52h gamma_b16 7: 0 gamma_table b16 value. gamma_b17 7: 0 default : 0d135 access : r/w 53h gamma_b17 7: 0 gamma_table b17 value. gamma_b18 7: 0 default : 0d143 access : r/w 54h gamma_b18 7: 0 gamma_table b18 value. gamma_b19 7: 0 default : 0d151 access : r/w 55h gamma_b49 7: 0 gamma_table b19 value. gamma_b20 7: 0 default : 0d159 access : r/w 56h gamma_b20 7: 0 gamma_table b20 value. gamma_b21 7: 0 default : 0d167 access : r/w 57h gamma_b21 7: 0 gamma_table b21 value. gamma_b22 7: 0 default : 0d175 access : r/w 58h gamma_b22 7: 0 gamma_table b22 value. gamma_b23 7: 0 default : 0d183 access : r/w 59h gamma_b23 7: 0 gamma_table b23 value. gamma_b24 7: 0 default : 0d191 access : r/w 5ah gamma_b24 7: 0 gamma_table b24 value. gamma_b25 7: 0 default : 0d199 access : r/w 5bh gamma_b25 7: 0 gamma_table b25 value. gamma_b26 7: 0 default : 0d207 access : r/w 5ch gamma_b26 7: 0 gamma_table b26 value. gamma_b27 7: 0 default : 0d215 access : r/w 5dh gamma_b27 7: 0 gamma_table b27 value. gamma_b28 7: 0 default : 0d223 access : r/w 5eh gamma_b28 7: 0 gamma_table b28 value. gamma_b29 7: 0 default : 0d232 access : r/w 5fh gamma_b29 7: 0 gamma_table b29 value. gamma_b30 7: 0 default : 0d239 access : r/w 60h gamma_b30 7: 0 gamma_table b30 value. gamma_b31 7: 0 default : 0d247 access : r/w 61h gamma_b31 7: 0 gamma_table b31 value. 62h gamma_b32 7: 0 default : 0d255 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 56 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. gamma register (indirect mapping to bank 00, registers 91h/92h) index mnemonic bits description gamma_b32 7: 0 gamma_table b32 value. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 57 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank = 00, registers b0h ~ ffh) scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description line_shift 7: 0 default : 0x00 access : r/w - 7 reserved. sel_v_clr 6 se lect vcounter clear by downcnt_eq1 or early_vs. - 5 reserved. vcr_ff_mode 4 enable output vsync follow input vsync mode. field_inv_vs 3 line shift vs field inverse. b0h line_shift_num[2:0] 2:0 line shift numbers. sync_control 7: 0 default : 0x08 access : r/w clk_dly[3:0] 7:4 output clock delay select. clk_inv 3 output clock invert enable. de_inv 2 output de invert enable. vs_inv 1 output vsync invert enable. b1h hs_inv 0 output hsync invert enable. sync_sel 7: 0 default : 0x00 access : r/w - 7:4 reserved. sel_vde 3 se lect vde output to vsync pin. sel_hde 2 se lect hde output to hsync pin. b2h data_skew 1:0 bus data skew select. svm_clk 7: 0 default : 0x10 access : r/w - 7 reserved. gb_swap 6 data bus g, b swap. rg_swap 5 data bus r, g swap. svm_clk_inv 4 sv m clock inverse. b3h svm_clkdly 3: 0 svm clock delay select. - 7: 0 default : - access : - b4h ~ bfh - 7:0 reserved. hsprdl_l 7: 0 default : - access : ro c0h hsprdl[7:0] 7: 0 number of system clock count at 512 hsyncs. hsprdl_m 7: 0 default : - access : ro c1h hsprdl[15:8] 7: 0 number of system clock count at 512 hsyncs. hsprdl_h 7: 0 default : - access : ro c2h hsprdl[23:16] 7: 0 number of system clock count at 512 hsyncs. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 58 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description ycdlyctl 7: 0 default : 0x00 access : r/w lnbf4_md 7 four line buffer mode. vsd_pipe 6 vs d pipe select. 0: original. 1: early pipe 2 cycle. - 5:3 reserved. c3h yc_dly_ctl 2: 0 yc delay control. 000: normal. 001: y early 1 cycle. 010: y early 2 cycles. 011: y early 3 cycles. 100: normal. 101: c early 1 cycle. 110: c early 2 cycles. 111: c early 3 cycles. vtotal_max_l 7: 0 default : 0xff access : r/w c4h total_max[7:0] 7: 0 vertical max total (lower 8 bits). vtotal_max_h 7: 0 default : 0x07 access : r/w - 7:3 reserved. c5h total_max[10:8] 2: 0 vertical max total (higher 3 bits). - 7: 0 default : - access : - c6h ~ c7h - 7:0 reserved. atgctrl 7: 0 default : 0x00 access : r/w maxr (ro) 7 max value flag for red channel (read only). 0: normal. 1: max value (255) value when agr = 0. output over max value (255) when agr = 1. maxg (ro) 6 max value flag for green channel (read only). 0: normal. 1: max value (255) value when agr = 0. output over max value (255) when agr = 1. c8h maxb (ro) 5 max value flag for blue channel (read only). 0: normal. 1: max value (255) value when agr = 0. output over max value (255) when agr = 1. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 59 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description ac_en 4 adc calibration enable. 0: disable. 1: enable. agr 3 auto gain result selection. 0: output has max/min value. 1: output is overflow/underflow. atgm 2 auto gain mode. 0: normal mode (result will be cleared every frame). 1: history mode (result remains not cleared till atge = 0). atgr (ro) 1 auto gain result ready. 0: result not ready. 1: result ready. atge 0 auto gain function enable. 0: disable. 1: enable. atgst 7: 0 default : - access : r/w vclp 7 v ideo auto gain mode. 0: rgb mode. 1: ypbpr mode. - 6 reserved. calr (ro) 5 calibration value flag for red channel. 0: normal. 1: calibration result (needs to increase offset) when ace=1. calg (ro) 4 calibration value flag for green channel. 0: normal. 1: calibration result (needs to increase offset) when ace=1. calb (ro) 3 calibration value flag for blue channel. 0: normal. 1: calibration result (needs to increase offset) when ace=1. c9h minr (ro) 2 min value flag for red channel. 0: normal. 1: min value (0) present when agr = 0, ace = 0. output under min value (0) when agr = 1, ace = 0. calibration result (needs to decrease offset) when ace = 1. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 60 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description ming (ro) 1 min value flag for green channel. 0: normal. 1: min value (0) present when agr = 0, ace = 0. output under min value (0) when agr = 1, ace = 0. calibration result (needs to decrease offset) when ace = 1. minb (ro) 0 min value flag for blue channel. 0: normal. 1: min value (0) present when agr = 0, ace = 0. output under min value (0) when agr = 1, ace = 0. calibration result (needs to decrease offset) when ace = 1. atfchsel 7: 0 default: 0x00 access : r/w - 7:6 reserved. atpchsel[1:0] 5:4 auto phase r/g/b channel select 00: r/g/b 3 channels 01: only r channel 10: only g channel 11: only b channel - 3 reserved. cah atgchsel[2:0] 2:0 auto gain r/g/b channel min/max value select. 000: r min value 001: g min value 010: b min value 011: r max value 100: g max value 101: b max value 11x: reserved atoctrl 7: 0 default : 0x00 access : r/w jitlr 7 j itter function left / right result for 86h and 87h. 0: left result. 1: right result. jits 6 j itter software clear. 0: not clear. 1: clear. - 5 reserved. cbh jitm 4 j itter function mode. 0: update every frame. 1: keep the history value. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 61 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description jitr 3 j itter function result (read only). 0: no jitter. 1: jitter present. atom 2 auto position function mode. 0: update every frame. 1: keep the history value. ator 1 auto position result ready (read only). 0: result ready. 1: result not ready. atoe 0 auto position function enable. 0: disable. 1: enable. disable-to-enable needs at least 2 frame apart for ready bit to settle. aovdv 7: 0 default : 0x00 access : r/w aovdv[3:0] 7:4 auto position valid data value. 0000: valid if data >= 0000 0000. 0001: valid if data >= 0001 0000. 0010: valid if data >= 0010 0000. 1111: valid if data >= 1111 0000. cch - 3:0 reserved. atgvalue (ro) 7: 0 default: - access : ro cdh atgvalue[7:0] 7:0 auto gain result based on 7ah[2:0]. aovst-l (ro) 7: 0 default : - access : ro ceh aovst [7:0] 7:0 auto position detected result vertical starting point. aovst-h (ro) 7: 0 default : - access : ro - 7:3 reserved. cfh aovst[10:8] 2: 0 see description for aovst [7:0]. aohst-l (ro) 7: 0 default : - access : ro d0h aohst[7:0] 7:0 auto position detected result horizontal starting point. aohst-h (ro) 7: 0 default : - access : db - 7:3 reserved. d1h sprgst[10:8] 2:0 image horizontal sample start point, count by input dot clock. aovend-l (ro) 7: 0 default : - access : ro d2h aovend[7:0] 7:0 auto position detected result vertical end point. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 62 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description aovend-h (ro) 7: 0 default : - access : ro - 7:3 reserved. d3h aovend[10:8] 2: 0 see description for aovend[7:0]. aohend-l (ro) 7: 0 default : - access : ro d4h aohend[7:0] 7:0 auto position detected result horizontal end point. aohend-h (ro) 7: 0 default : - access : ro - 7:4 reserved. d5h aohend[11:8] 2: 0 see description for aohend[7:0]. jlr-l (ro) 7: 0 default : - access : ro d6h jlr[7:0] 7: 0 jitter function detected left/right most point state (previous frame) depend on reg_7bh[7]. jlr-h (ro) 7: 0 default : - access : ro - 7:3 reserved. d7h jlr[10:8] 2: 0 see description for jlr[7:0]. anrf 7: 0 default : - access : ro - 7:6 reserved. hnen 5 h igh level noise reduction enable. 0: disable. 1: enable. bgen 4 background noise reduction enable. 0: disable. 1: enable. - 3 reserved. d8h anlv[2:0] 2:0 auto noise level, 000: noise level = 1, 001: noise level = 2, 010: noise level = 4, 011: noise level = 8, 100: noise level = 9, 101: noise level = 10, 110: noise level = 12, 111: noise level = 16. atpgth 7: 0 default : 0x01 access : r/w d9h atpgth[7:0] 7:0 auto phase gray scale threshold for atpv3 when atpn4 = 0. dah atptth 7: 0 default : 0x10 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 63 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description atptth[7:0] 7:0 auto phase text threshold for atpv4. atpctrl 7: 0 default : 0x00 access : r/w atp_fltrmd 7 0 : disable auto-position filter mode. 1: enable auto-position filter mode. gry (ro) 6 g ray scale detect (read only). txt (ro) 5 text detect (read only). apmask[2:0] 4: 2 nose mask. 000: mask 0 bit, default value. 001: mask 1 bit. 010: mask 2 bit. 011: mask 3 bit. 100: mask 4 bit. 101: mask 5 bit. 110: mask 6 bit. 111: mask 7 bit. atpr (ro) 1 auto phase result ready. 0: result not ready. 1: result ready. dbh atpe 0 auto phase function enable. 0: disable. 1: enable. atpv1 (ro) 7: 0 default : - access : ro dch atpvalue[7:0] 7:0 auto phase value. atpv2 (ro) 7: 0 default : - access : ro ddh atpvalue[15:8] 7: 0 see description for atpvalue[7:0]. atpv3 (ro) 7: 0 default : - access : ro deh atpvalue[23:16] 7: 0 see description for atpvalue[7:0]. atpv4 (ro) 7: 0 default : - access : ro dfh atpvalue[31:24] 7: 0 see description for atpvalue[7:0]. pdmd0 7: 0 default : 0x00 access : r/w e0h gclk[1:0] 7: 6 gated clock for sram. 00: normal. 01: v blank. 10: h blank and v blank. 11: reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 64 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description auxclk_gat 5 0 : enable mvd mcu-support clock. 1: disable mvd mcu-support clock. cmbclk_gat 4 0 : enable mvd comb-filter clock. 1: disable mvd comb-filter clock. - 3 reserved. eoclk_inv 2 external osd sample clock inverting. idclk_inv 1 s caler input sample clock inverting. fscclk_inv 0 s ub-carrier clock inverting. pdmd1 7: 0 default : 0x00 access : r/w pdall 7 all chip power down. biuclk_gat 6 0 : enable register interface clock. 1: disable register interface clock. osdclk_gat 5 0 : enable osd clock. 1: disable osd clock. pcclk_gat 4 0 : enable crt output suppot clock. 1: disable crt output suppot clock. adcclk_gat 3 0 : enable 3-channel adc digital clock. 1: disable 3-channel adc digital clock. vdclk_gat 2 0 : enable ccir and mvd interface clock. 1: disable ccir and mvd interface clock. idclk_gat 1 0 : enable scaler clock. 1: disable scaler clock. e1h fscclk_gat 0 0 : enable mvd digital front-end clock. 1: disable mvd digital front-end clock. swrst0 7: 0 default : 0x00 access : r/w regr 7 register reset. 0: normal operation. 1: reset register. adcr 6 adc reset. 0: normal operation. 1: reset adc. ipr 5 digital input port reset. 0: normal operation. 1: reset. e2h op1r 4 s caler reset. 0: normal operation. 1: reset. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 65 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description op2r 3 display port reset. 0: normal operation. 1: reset. - 2 reserved. osdr 1 internal osd reset. 0: normal operation. 1: reset internal osd. swr 0 s oftware reset (reset all digital core except system registers). 0: normal operation. 1: reset. swrst1 7: 0 default : 0x00 access : r/w vfer 7 v ideo decoder front end reset. 0: normal operation. 1: reset. vcfr 6 v ideo decoder comb filter reset. 0: normal operation. 1: reset. mcur 5 embedded mcu reset. 0: normal operation. 1: reset. mcur 4 g mc digital tune reset. 0: normal operation. 1: reset. e3h - 3:0 reserved. isovrd 7: 0 default : 0x00 access : r/w sl 7 s hift line. 0: shift line method 0. 1: shift line method 1 for interlace mode. cshs 6 hsync in coast. 0: hsyout (recommended). 1: re-shaped hsync. uvsp 5 use r defined input vsync polarity, active when ivsj =1. 0: active low. 1: active high. e4h ivsj 4 input vsync polarity judgment. 0: use result of internal circuit detection. 1: defined by user (uvsp). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 66 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description uhsp 3 use r defined input hsync polarity, active when ivsj =1. 0: active low. 1: active high. ihsj 2 input hsync polarity judgment. 0: use result of internal circuit detection. 1: defined by user (uhsp). uint 1 use r defined non-interlace/interlace, active when intj = 1. 0: non-interlace. 1: interlace. intj 0 interlace judgment. 0: use result of internal circuit detection. 1: defined by user (uint). mdctrl 7: 0 default : 0x00 access : r/w ip_test_md 7:6 ip test-bus selection. verr 5 v ideo ccir656 error correct. 0: disable. 1: enable. field_absmd 4 field postion absolute value mode. vfiv 3 v ideo field inversion. 0: normal. 1: invert. vexf 2 v ideo external field. 0: use result of internal circuit detection. 1: use external field. intf 1 interlace field detect method select. 0: use the hsync numbers of a field to judge. 1: use the relationship of vsync and hsync to judge. e5h ifi 0 interlace field inverting. 0: normal. 1: invert. hspw (ro) 7: 0 default : - access : ro e6h hs_pw 7: 0 hs pulse width vfree 7: 0 default : 0x00 access : r/w autoopcoast_clr 7 se t auto-coast-for-output status. autoopcoast 6 enable auto-coast-for-output. e7h min_vtt[5:0] 5:0 minimum vtt to free-run. e8h hstol 7: 0 default : 0x05 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 67 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description vs2hs (ro) 7 input vsync too close to input hsync. ln4_detmd 6 4 line detect mode for hs, de. hstol[5:0] 5: 0 hsync tolerance. 5: default value. vstol 7: 0 default : 0x01 access : r/w autonosignal_clr 7 se t auto-no-signal status. autonosignal 6 enable auto-no-signal function. htt_filtermd 5 h tt filter mode. hvtt_lose_md 4 hv tt lose mode. 0: original. 1: new by wdt sample. e9h vs_tol[3:0] 3: 0 vsync tolerance. 1: default value. hsprd_l 7: 0 default : - access : ro eah hsprd[7:0] 7:0 input horizontal period, count by reference clock. hsprd_h 7: 0 default : - access : ro - 7:5 reserved. ebh hsprd[12:8] 4: 0 see description for hsprd[7:0]. vtotal_l 7: 0 default : - access : ro ech vtotal[7:0] 7:0 input vertical total length, count by hsync. vtotal_h 7: 0 default : - access : ro - 7:3 reserved. edh vtotal[10:8] 2: 0 see description for vtotal[7:0]. pdmd2 7: 0 default : 0x60 access : rw mcuclk_sel 7 mcu clock source select. 0: xtal. 1: mpll divided. mcudiv 6:4 mcu clock divided by mpll. 000: 4. 001: 6. 010: 8. 011: 10. 100: 12. 101: 14. 110: 16. eeh - 3:1 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 68 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description cc_gat 0 comb clock gating. 1: gating mode. 0: no gating. status2 (ro) 7: 0 default : - access : ro htt_chg_cs 7 htotal change in csog. - 6 reserved. std_pal 5 0: ntsc. 1: pal. csd 4 csync detected status. 0: input is not csync. 1: input is detected as csync. intm 3 interlace / non-interlace detecting result by this chip. 0: non-interlace. 1: interlace. intf 2 input odd/even field detecting result by this chip. 0: even. 1: odd. ihsp 1 incoming input hsync polarity detecting result by this chip. 0: active low. 1: active high. efh ivsp 0 incoming input vsync polarity detecting result by this chip. 0: active low. 1: active high. chip_id 7: 0 default : 0x00 access : ro f0h chip_id[7:0] 7:0 chip id is 70h chip_version 7: 0 default : 0x01 access : ro f1h chip_ver[7:0] 7: 0 version is 01h - 7: 0 default : - access : - f2h ~ f3h - 7:0 reserved. tristate 7: 0 default : 0x00 access : r/w - 7:5 reserved. obbus_tri 4 output bus tristate. vs_tri 3 output vsync tristate. hsy_tri 2 output hsync tristate. f4h de_tri 1 output de tristate. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 69 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. scaler register (bank=00, registers b0h ~ ffh) index mnemonic bits description clk_tri 0 output clk tristate. - 7: 0 default : - access : - f7h ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 70 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) analog register (bank = 01) index name bits description - 7: 0 default : - access : - 01h ~ 4fh - 7:0 reserved. lpf_tap1 7: 0 default : 0x00 access : r/w round_sel 7:6 round select. 50h lpftap_1[5:0] 5:0 lpf coefficient 1. (2 s complement: -32 ~ 31) lpf_tap2 7: 0 default : 0x 00 access : r/w vsd_dith 7 v sd dither method. vsd_seed_sel 6 vs d dither seed select. 51h lpftap_2[5:0] 5:0 lpf coefficient 2. lpf_tap3 7: 0 default : 0x00 access : r/w vsd_round_e n 7 vsd rounding enable. seed_sel 6 lpf dither seed select. 52h lpftap_3[5:0] 5:0 lpf coefficient 3. lpf_tap4 7: 0 default : 0x00 access : r/w csc_dith_en 7 csc dither enable. csc_seed_sel 6 csc dither seed select. 53h lpftap_4[5:0] 5:0 lpf coefficient 4. lpf_tap5 7: 0 default : 0x00 access : r/w - 7:6 reserved. 54h lpftap_5[5:0] 5:0 lpf coefficient 5. lpf_ctl 7: 0 default : 0x00 access : r/w csc_en 7 csc enable. 0: disable. 1: enable. 55h lpftap_en 6 lpftap enable. 0: disable. 1: enable. fcc_cb_1t 7: 0 default : 0x00 access : r/w 56h fcc_cb_1t[7:0] 7:0 fcc cb 1t. fcc_cr_1t 7: 0 default : 0x00 access : r/w 57h fcc_cr_1t[7:0] 7:0 fcc cr 1t. 58 h fcc_cb_2t 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 71 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description fcc_cb_2t[7:0] 7:0 fcc cb 2t. fcc_cr_2t 7: 0 default : 0x00 access : r/w 59h fcc_cr_2t[7:0] 7:0 fcc cr 2t. fcc_cb_3t 7: 0 default : 0x00 access : r/w 5ah fcc_cb_3t[7:0] 7:0 fcc cb 3t. fcc_cr_3t 7: 0 default : 0x00 access : r/w 5bh fcc_cr_3t[7:0] 7:0 fcc cr 3t. fcc_cb_4t 7: 0 default : 0x00 access : r/w 5ch fcc_cb_4t[7:0] 7:0 fcc cb 4t. fcc_cr_4t 7: 0 default : 0x00 access : r/w 5dh fcc_cr_4t[7:0] 7:0 fcc cr 4t. fcc_cb_5t 7: 0 default : 0x00 access : r/w 5eh fcc_cb_5t[7:0] 7:0 fcc cb 5t. fcc_cr_5t 7: 0 default : 0x00 access : r/w 5fh fcc_cr_5t[7:0] 7:0 fcc cr 5t. fcc_cb_6t 7: 0 default : 0x00 access : r/w 60h fcc_cb_6t[7:0] 7:0 fcc cb 6t. fcc_cr_6t 7: 0 default : 0x00 access : r/w 61h fcc_cr_6t[7:0] 7:0 fcc cr 6t. fcc_cb_7t 7: 0 default : 0x00 access : r/w 62h fcc_cb_7t[7:0] 7:0 fcc cb 7t. fcc_cr_7t 7: 0 default : 0x00 access : r/w 63h fcc_cr_7t[7:0] 7:0 fcc cr 7t. fcc_cb_8t 7: 0 default : 0x00 access : r/w 64h fcc_cb_8t[7:0] 7:0 fcc cb 8t. fcc_cr_8t 7: 0 default : 0x00 access : r/w 65h fcc_cr_8t[7:0] 7:0 fcc cr 8t. white_slop 7: 0 default : 0x80 access : r/w 66h white_slop[7:0] 7:0 white contrast adjust slope. >80h : slope >1. =80h : slope=1. <80h : slop <1. 67h black_slop 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 72 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description black_slop [7:0] 7:0 black contrast adjust slope. >80h : slope >1. =80h : slope=1. <80h : slop <1. fcc_win1 7: 0 default : 0x00 access : r/w cb_d1u[1:0] 7:6 cb d1u. cb_d1d[1:0] 5:4 cb d1d. cr_d1u[1:0] 3:2 cr d1u. 68h cr_d1d[1:0] 1:0 cr d1d. fcc_win2 7: 0 default : 0x00 access : r/w cb_d2u[1:0] 7:6 cb d2u. cb_d2d[1:0] 5:4 cb d2d. cr_d2u[1:0] 3:2 cr d2u. 69h cr_d2d[1:0] 1:0 cr d2d. fcc_win3 7: 0 default : 0x00 access : r/w cb_d3u[1:0] 7:6 cb d3u. cb_d3d[1:0] 5:4 cb d3d. cr_d3u[1:0] 3:2 cr d3u. 6ah cr_d3d[1:0] 1:0 cr d3d. fcc_win4 7: 0 default : 0x00 access : r/w cb_d4u[1:0] 7:6 cb d4u. cb_d4d[1:0] 5:4 cb d4d. cr_d4u[1:0] 3:2 cr d4u. 6bh cr_d4d[1:0] 1:0 cr d4d. fcc_win5 7: 0 default : 0x00 access : r/w cb_d5u[1:0] 7:6 cb d5u. cb_d5d[1:0] 5:4 cb d5d. cr_d5u[1:0] 3:2 cr d5u. 6ch cr_d5d[1:0] 1:0 cr d5d. fcc_win6 7: 0 default : 0x00 access : r/w cb_d6u[1:0] 7:6 cb d6u. cb_d6d[1:0] 5:4 cb d6d. cr_d6u[1:0] 3:2 cr d6u. 6dh cr_d6d[1:0] 1:0 cr d6d. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 73 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description fcc_win7 7: 0 default : 0x00 access : r/w cb_d7u[1:0] 7:6 cb d7u. cb_d7d[1:0] 5:4 cb d7d. cr_d7u[1:0] 3:2 cr d7u. 6eh cr_d7d[1:0] 1:0 cr d7d. fcc_win8 7: 0 default : 0x00 access : r/w cb_d8u[1:0] 7:6 cb d8u. cb_d8d[1:0] 5:4 cb d8d. cr_d8u[1:0] 3:2 cr d8u. 6fh cr_d8d[1:0] 1:0 cr d8d. fcc_win9 7: 0 default : 0x00 access : r/w - 7:6 reserved. cb_d9[2:0] 5:3 cb d9. 70h cr_d9[2:0] 2:0 cr d9. - 7: 0 default : - access : - 71h - 7:0 reserved. fcc_k1k2 7: 0 default : 0xff access : r/w fcc_k_t1[3:0] 7 fcc k t1. 72h fcc_k_t2[3:0] 0 fcc k t2. fcc_k3k4 7: 0 default : 0xff access : r/w fcc_k_t3[3:0] 7 fcc k t3. 73h fcc_k_t4[3:0] 0 fcc k t4. fcc_k5k6 7: 0 default : 0xff access : r/w fcc_k_t5[3:0] 7 fcc k t5 74h fcc_k_t6[3:0] 0 fcc k t6. fcc_k7k8 7: 0 default : 0xff access : r/w fcc_k_t7[3:0] 7 fcc k t7. 75h fcc_k_t8[3:0] 0 fcc k t8. fcc_ctrl 7: 0 default : 0x00 access : r/w m_fcc_t9 7 fcc t9 enable. m_fcc_t8 6 fcc t8 enable. m_fcc_t7 5 fcc t7 enable. 76h m_fcc_t6 4 fcc t6 enable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 74 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description m_fcc_t5 3 fcc t5 enable. m_fcc_t4 2 fcc t4 enable. m_fcc_t3 1 fcc t3 enable. m_fcc_t1_t2 0 fcc t1 and t2 enable. app_ctrl 7: 0 default : 0x00 access : r/w - 7 reserved. mcme 6 cti median filter enable. 0: disable. 1: enable. mcen 5 cti enable. 0: disable. 1: enable. mlme 4 lti median fitler enable. 0: disable. 1: enable. mlen 3 lti enable. 0: disable. 1: enable. mpen 2 band1 and band2 peak enable. 0: disable. 1: enable. 77h - 1:0 reserved. peak_band1 7: 0 default : 0x08 access : r/w band1_step[1:0] 7:6 band 1 step adjust. 00: 1. 01: 2. 10: 3. 11: 4. 78h band1_coef[5:0] 5:0 band 1 coefficient. (xxx.xxx) peak_band2 7: 0 default : 0x08 access : r/w 79h band2_step[1:0] 7:6 band 2 step adjust. 00: 1. 01: 2. 10: 3. 11: 4. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 75 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description band2_coef[5:0] 5:0 band 2 coefficient. (xxx.xxx) lti 7: 0 default : 0x08 access : r/w lti_step[1:0] 7:6 lti step adjust. 00: 1. 01: 2. 10: 3. 11: 4. 7ah lti_coef[5:0] 5:0 lti coefficient. (xxx.xxx) term_sel 7: 0 default : 0x00 access : r/w p_t1[1:0] 7:6 peaking term1 select. 00, 01: band 1. 10: band 2. 11: lti. p_t2[1:0] 5:4 peaking term2 select. 00, 01: band 1. 10: band 2. 11: lti. p_t3[1:0] 3:2 peaking term3 select. 00, 01: band 1. 10: band 2. 11: lti. 7bh p_t4[1:0] 1:0 peaking term4 select. 00, 01: band 1. 10: band 2. 11: lti. coring 7: 0 default : 0x00 access : r/w cth_2[3:0] 7:4 coring threshold 2. 7ch cth_1[3:0] 3:0 coring threshold 1. cti 7: 0 default : 0x08 access : r/w - 7 reserved. 7dh cti_step[1:0] 6:5 cti step adjust. 00: 1. 01: 2. 10: 3. 11: 4. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 76 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description cti_coef[4:0] 4:0 cti coefficient. (xx.xxx) vip_y_ctrl 7: 0 default : 0x00 access : r/w - 7:2 reserved. wleen 1 white level extension enable. 0: disable. 1: enable. 7eh bleen 0 black level extension enable. 0: disable. 1: enable. white_start 7: 0 default : 0x80 access : r/w 7fh white_start[7:0] 7:0 white contrast adjust starting point (must > or =80h); active range is from white_start[7:0] to ffh. black_start 7: 0 default : 0x00 access : r/w 80h black_start[7:0] 7:0 black contrast adjust starting point (must < 80h); active range is from 00h to black_start[7:0] ege_band1_pos 7: 0 default : 0x00 access : r/w 81h egeband1_pos[7:0] 7:0 edge band 1 coefficient (positive threshold for median filter max pixel). ege_band1_n eg 7: 0 default : 0x00 access : r/w 82h egeband1_neg[7:0] 7:0 edge band 1 coefficient (negative threshold for median filter min pixel). ege_band2_pos 7: 0 default : 0x00 access : r/w 83h egeband2_pos[7:0] 7:0 edge band 2 coefficient (positive threshold for median filter max pixel). ege_band2_n eg 7: 0 default : 0x00 access : r/w 84h egeband2_neg[7:0] 7:0 edge band 2 coefficient (negative threshold for median filter min pixel). bri 7: 0 default : 0x00 access : r/w 85h bri[7:0] 7:0 window brightness (2 s complement: -128 ~ 127). ege_lti_pos 7: 0 default : 0xff access : r/w 86h egelti_pos[7:0] 7:0 edge lti coefficient (positive threshold for median filter max pixel). ege_lti_n eg 7: 0 default : 0xff access : r/w 87h egelti_neg[7:0] 7:0 edge lti coefficient (negative threshold for median filter min pixel). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 77 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description yc_lpf 7: 0 default : 0x00 access : r/w c_lpf_md[1:0] 7:6 c lpf mode. 00: original. 01: 11. 10: 121. 11: 161. y_lpf_md[1:0] 5: 4 y lpf mode. b1den 3 band 1 differentiate enable. b2den 2 band 2 differentiate enable. 88h - 1:0 reserved. - 7: 0 default : - access : - 89h - 7:0 reserved. y_coring_ctrl 7: 0 default : 0x00 access : r/w hps_en 7 coring as high pass. y_tbl_step 6: 4 y coring table step. pc_mode 3 coring in pc mode. y_dither 2 y coring dither enable. y_coring_band2_en 1 y coring band2 enable. 8ah y_coring_band1_en 0 y coring band1 enable. c_coring_ctrl 7: 0 default : 0x00 - 7 reserved. c_tbl_step 6:4 c coring table step. - 3 reserved. c_dither 2 c coring dither enable. c_coring_band2_en 1 c coring band2 enable. 8bh c_coring_band1_en 0 c coring band1 enable. coring_tbl 1 7: 0 default : 0x00 access : r/w 8ch coring_table1[7:0] 7:0 coring table 1. coring_tbl 2 7: 0 default : 0x00 8dh coring_table2[7:0] 7:0 coring table 2. coring_tbl 3 7: 0 default : 0x00 8eh coring_table3[7:0] 7:0 coring table 3. coring_tbl 4 7: 0 default : 0x00 8fh coring_table4[7:0] 7:0 coring table 4. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 78 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description saradc_ctrl 7: 0 default : 0x40 access : r/w sar_sngl_chnl 1:0 channel selection in single channel mode. - 3:2 reserved. sar_sngl 4 s ingle channel mode enable. only sample channel at bit[1:0] sar_freerun 5 s aradc sample mode. 1: freerun mode. 0: one shot mode. - 6 reserved. sar_start 7/w saradc sample start. 90h sar_rdy 7/r saradc sample ready. saradc_sam prd 7: 0 default : 0x20 access : r/w 91h cksamp_prd 7: 0 saradc input sample period in one shot mode. real_samp_prd = cksamp_pr x 4 saradc_aisel 7: 0 default : 0x00 access : r/w sar_aisel 3: 0 sar_aisel[3:0]: input select of pad_sar_gpio sar_aisel[i]=1b 0: digital gpio input sar_aisel[i]=1b 1: sar adc analog input 92h - 7:4 reserved - 7: 0 default : - access : - 93h - 7:0 reserved. sar_ch1_u pb 7: 0 default : 0x00 access : r/w - 7:6 reserved. 94h reg_sar_ch1_upb [5:0] 5:0 the voltage upper bound in mcu sleep mode for channel 1 keypad wake up. sar_ch1_lo b 7: 0 default : 0x00 access : r/w - 7:6 reserved. 95h reg_sar_ch1_lob [5:0] 5:0 the voltage lower bound in mcu sleep mode for channel 1 keypad wake up. sar_ch2_u pb 7: 0 default : 0x00 access : r/w - 7:6 reserved 96h reg_sar_ch2_upb [5:0] 5:0 the voltage upper bound in mcu sleep mode for channel 2 keypad wake up. sar_ch2_lo b 7: 0 default : 0x00 access : r/w 97h - 7:6 reserved mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 79 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description reg_sar_ch2_lob [5:0] 5:0 the voltage lower bound in mcu sleep mode for channel 2 keypad wake up. sar_ch3_u pb 7: 0 default : 0x00 access : r/w - 7:6 reserved 98h reg_sar_ch3_upb [5:0] 5:0 the voltage upper bound in mcu sleep mode for channel 3 keypad wake up. sar_ch3_lo b 7: 0 default : 0x00 access : r/w - 7:6 reserved. 99h reg_sar_ch3_lob [5:0] 5:0 the voltage lower bound in mcu sleep mode for channel 3 keypad wake up. - 7: 0 default : - access : - 9ah ~ 9bh - 7:0 reserved. adc_md_ctrl 7: 0 default : 0x00 access : r/w adc_dctrl 7:6 reserved for adc dctrl. gshift_r 5 1 : enable adc r gain range shift for vd mode. gshift_g 4 1 : enable adc g gain range shift for vd mode. gshift_b 3 1 : enable adc b gain range shift for vd mode. 9ch adc_vctrl 2:0 adc voltage control (recommend setting = 3 b011). - 7: 0 default : - access : - 9dh - 7:0 reserved. cal_ctrl3 7: 0 default : 0x00 access : r/w - 7 reserved. cal_stswen 6 1 : enable write to internal cal registers through status_cal. cal_swov 5: 4 00: normal mode. 01: switch adc input to offset cal reference voltage. 10: reserved. 11: reserved. cal_hold 3 1 : hold current cal result for display. cal_input 2 0 : cal to internal offset reference voltage. 1: cal to adc input. cal_hys 1 1 : enable cal update hytheresis. 9eh doffs_en 0 1 : enable digital offset adjustment. adctout 7: 0 default : 0x00 access : r/w - 7:4 reserved. 9fh adctout_sync 3 1 : enable adc test out sync to ckext. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 80 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description adctout_div 2: 0 select adc test out decimation ratio (1~8). rg_drv 7: 0 default : 0x55 access : r/w g[7:6]_drv[1:0] 7:6 pad g[7:4] driving select. g[5:4]_drv[1:0] 5:4 pad g[3:0] driving select. r[3:2]_drv[1:0] 3:2 pad r[7:4] driving select. a0h r[1:0]_drv[1:0] 1:0 pad r[3:0] driving select. rg_drv 7: 0 default : 0x55 access : r/w hs_drv[1:0] 7:6 pad hsync driving select. vs_drv[1:0] 5:4 pad vsync driving select. b[7:4]_drv[1:0] 3:2 pad b[7:4] driving select. a1h b[3:0]_drv[1:0] 1:0 pad b[3:0] driving select. rg_drv 7: 0 default : 0x55 access : r/w pwm2_drv[1:0] 7:6 pad pwm2 driving select. pwm1_drv[1:0] 5:4 pad pwm1 driving select. clk_drv[1:0] 3:2 pad clk driving select. a2h de_drv[1:0] 1:0 pad de driving select. epd_r 7: 0 default : 0x00 access : r/w a3h epd_r[7:0] 7:0 enable pull down in r channel. epd_g 7: 0 default : 0x00 access : r/w a4h epd_g[7:0] 7:0 enable pull down in g channel. epd_b 7: 0 default : 0x00 access : r/w a5h epd_b[7:0] 7:0 enable pull down in b channel. epd_r 7: 0 default : 0x00 access : r/w - 7:6 reserved. epd_pwm2 5 enable pull down in pwm2 pad. epd_pwm1 4 enable pull down in pwm2 pad. epd_clk 3 enable pull down in clk pad. epd_de 2 enable pull down in de pad. epd_hs 1 enable pull down in hsync pad. a6h epd_vs 0 enable pull down in vsync pad. - 7: 0 default : - access : - a7h ~ aah - 7:0 reserved. abh vdac_adj2 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 81 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description - 7:5 reserved. ed[4:0] 4:0 testing control for voltage dac. - 7: 0 default : - access : - ach ~ afh - 7:0 reserved. svmctl0 7: 0 default : 0x50 access : r/w smen 7 sv m main window enable. smte 6 sv m main window tap enable. smft[1:0] 5: 4 svm main window filter tap. 00: 2 tap. 01: 3 tap. 10: 4 tap. 11: 5 tap. b0h - 3:0 reserved. svmctl1 7: 0 default : 0x08 access : r/w osdy 7 osd color space. 0: osd color space. 1: osd is yuv color space. sinv 6 s mv polarity invert. 0: normal. 1: invert. svmbys[1:0] 5: 4 svm bypass y select. 0x: smv data. 10: original y data. 11: y with tap filter. b1h scoring[3:0] 3: 0 svm coring. svmlmt 7: 0 default : 0x70 access : r/w b2h svmlmt[7:0] 7: 0 svm limit. smsg 7: 0 default : 0x4a access : r/w - 7 reserved. b3h smstep[2:0] 6: 4 svm main window step. 000: 1 step. 001: 2 steps. 111: 8 steps. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 82 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description smgain[3:0] 3: 0 svm main window gain. 0000: 1/16/ 0001: 1/8. 0010: 1/4. 0011: 3/8. 0100: 1/2. 0101: 5/8. 0110: 3/4. 0111: 1. 1110: 9/8. 1001: 5/4. 1010: 3/2. 1011: 2. 1100: 3. 1101: 4. 1110: 5. 1111: 8. svmadj 7: 0 default : 0x26 access : r/w - 7 reserved. svmpip[1:0] 6: 5 svm pipe adjust. b4h svmdly[4:0] 4: 0 svm delay adjust. 00000: 8 clocks ahead. 00001: 7 clocks ahead. 11111: delay 23 clocks. overlap _sel 7: 0 default : 0x00 access : r/w svm_sep_dly 7 sv m separate delay enable. overlap_sel[1:0] 6:5 overlap select. 00: average. 01: no action. 10: keep slow down result. 11: keep speed up result. b5h svm_sd_dly[4:0] 4: 0 svm slow down delay. lck_thr_fpll 7: 0 default : 0x03 access : r/w b6h lck_thr[7:0] 7:0 lock threshold. lmt_lpll_ofst_l 7: 0 default : 0xf0 access : r/w b7h lmt_lpll_ofst[7:0] 7:0 limit lpll offset low byte. b8 h lmt_lpll_ofst_h 7: 0 default : 0xff access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 83 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description lmt_lpll_ofst [15:8] 7:0 limit lpll offset high byte. coef_fpll 7: 0 default : 0x50 access : r/w tune_coef[3:0] 7:4 tune coefficient. b9h tune_coef_rk[3:0] 3:0 tune coefficient rk. rk_hold_gain_l 7: 0 default : 0x00 access : r/w bah rk_hold_gain[7:0] 7:0 rk hold gain low byte. rk_hold_gain_h 7: 0 default : 0x00 access : r/w - 7:4 reserved. bbh rk_hold_gain [11:8] 3:0 rk hold gain high byte. lpll_stlmt_l 7: 0 default : 0x00 access : r/w beh lpll_stlmt[7:0] 7:0 fpll set limit low byte. lpll_stlmt_h 7: 0 default : 0x00 access : r/w bfh lpll_stlmt[15:8] 7:0 fpll set limit high byte. tune_frame_no 7: 0 default : 0x00 access : r/w bnd_ovwr_en 7 bonding over-write enable. - 6:2 reserved. c0h tune_frame_no 1:0 frame pll tune per tune_frame numbers bnd_rst 7: 0 default : 0x7f access : r/w mcu_sel_ovwr 7 se lect internal mcu disable. c1h bnd_rst[6:0] 6:0 bonding reset. lmt_add_nm b 7: 0 default : 0x17 access : r/w c2h lmt_add_nmb[7:0] 7:0 limit adjust number in acc_fpll mode. ivs_diff_th r 7: 0 default : 0x03 access : r/w c3h ivs_diff_thr[7:0] 7:0 input v.s. different thresholds. ivs_stalbe_th r 7: 0 default : 0x03 access : r/w c4h ivs_stb_thr[7:0] 7:0 input v.s. stable thresholds. ch_ch_mod e 7: 0 default : 0x02 access : r/w - 7:6 reserved. ch_ch_md1 5 acc fpll mode 1. - 4 reserved. c5h fpll_dis 3 fpll stop. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 84 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description - 2 reserved. add_line_sel 1 se lect add line into frame or pixel into line. ch_ch_md0 0 acc fpll mode 0. acc1_sel 7: 0 default : 0x00 access : r/w - 7:5 reserved. tune_clk_ff 4 tune clock enable when ff mode. - 3:2 reserved. c6h acc1_sel[1:0] 1: 0 select modify numbers. 00: 3/4 diff numbers. 01: 1/2 diff numbers. others:1/4 diff numbers. ivs_prd_num_l 7: 0 default : 0x03 access : r/w c7h ivs_prd_num[7:0] 7:0 count number per input v.s low byte. ivs_prd_num_h 7: 0 default : 0x03 access : r/w - 7:4 reserved. c8h ivs_prd_num[11:8] 3:0 count number per input v.s 4 high bytes. pol_set0 7: 0 default : 0x00 access : r/w pol_out_inv 7 pol output invert. cah pol_tp 6:0 pol transition point. pol_set1 7: 0 default : 0x00 access : r/w - 7:5 reserved. pol_sel 4 0 : vsync frequency pol. 1: hsync frequency pol. pol_pvi_10in 3 pol output to seq_mod pin if efh[7] = 0. cbh - 2:0 reserved. scal_act 7: 0 default : 0x00 access : r/w - 7:6 reserved. tc_clk_div2 5 tc clock divide 2. - 4 reserved. line_act_d1l 3 line active delay one line time. line_act_en 2 tcon line_extract mode work with digital v_scaling. cch - 1:0 reserved. gpo_oev2_width 7: 0 default : 0x54 access : r/w cdh gpo_oev2_dis 7 oev2 disable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 85 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description gpo_oev2_width [6:0] 6:0 oev2 pulse width. gpo_oev3_width 7: 0 default : 0x54 access : r/w gpo_oev3_dis 7 oev3 disable. ceh gpo_oev3_width [6:0] 6:0 oev3 pulse width. gpo_oev_ delta 7: 0 default : 0x54 access : r/w - 7:4 reserved. cfh gpo_oev_ delta[3:0] 3:0 adjust oev distance. ptc_mode1 7: 0 default : 0x8c access : r/w tc_md 7 tc signal output enable. 0: disable set low. 1: enable. oev_delta_en 6 oev distance adjust enable. dou_extr_md[1:0] 5: 4 00: normal mode. 01: paranoma extract mode. 10: full extract mode. 11: line duplicate mode. frame_inv_en 3 0 : disable. 1: enable. early_vs 2 early vs. field_sel 1 se lect field inverse from ip. d0h ln_shift 0 field line shift enable. ptc_mode2 7: 0 default : 0x3e access : r/w tcclk_conf[1:0] 7: 6 7: 13 clk swap. 6: 3 clk inverse. seq_md 5 0 : single clock output mode. 1: three clock output mode. tcclk_md 4 se lect 3tc clk or 1 tc clk. sthlr_sel 3 0 : sthr. 1: sthl. stvlr_sel 2 0 : stvr. 1: stvl. d1h l_r 1 0 : l_r equal 0. 1: l_r equal 1. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 86 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description u_d 0 0 : u_d=0. 1: u_d=1. ptc_mode3 7: 0 default : 0x84 access : r/w set_tcclk23_value 7 se t tcclk23 high/low. lg_md 6 lg_panel mode enable. df_ext_ln 5 different frame, different extract line mode. 0: disable. 1: enable. ln_dup_md[1:0] 4:3 duplicate 2/3 line mode. 4: oev3 enable. 3: oev2 enable. field_in_sel 2 se lect field source from op2 or free-run. line_inv_dis 1 line inverse disable. 0: enable. 1: disable. d2h frp_vcom_inv 0 v com inverse to frp. ln_extr_cnt_lmt 7: 0 default : 0xdd access : r/w ln_extr_cnt_lmt2 7:4 line extract/duplicate counter 2. d3h ln_extr_cnt_lmt1 3:0 line extract/duplicate counter 1. ln_extr_set1_h 7: 0 default : 0x2f access : r/w d4h ln_extr_set1[7:0] 7:0 line extract/duplicate set 1 high byte. ln_extr_set1_l 7: 0 default : 0xef access : r/w d5h ln_extr_set1[15:8] 7:0 line extract/duplicate set 1 low byte. ln_extr_set2_h 7: 0 default : 0x1f access : r/w d6h ln_extr_set2[7:0] 7:0 line extract/duplicate set 2 high byte. ln_extr_set2_l 7: 0 default : 0xe7 access : r/w d7h ln_extr_set2[15:8] 7:0 line extract/duplicate set 2 low byte. extr_stt_ln 1 7: 0 default : 0x02 access : r/w d8h extr_stt_ln1[7:0] 7:0 line extract/duplicate start line 1. extr_end_ln 1 7: 0 default : 0x30 access : r/w d9h extr_end_ln1[7:0] 7:0 line extract/duplicate end line 1. extr_stt_ln 2 7: 0 default : 0x50 access : r/w dah extr_stt_ln2[7:0] 7:0 line extract/duplicate start line 2. extr_end_ln 2 7: 0 default : 0x77 access : r/w dbh extr_end_ln2[7:0] 7:0 line extract/duplicate end line 2. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 87 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description gpo_frp_tran 7: 0 default : 0x13 access : r/w out_inv 7 output inverse. gpo_frp_tran_mult [1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. dch gpo_frp_tran[4:0] 4:0 frp transition position. gpo_sth_stt 7: 0 default : 0x46 access : r/w out_inv 7 output inverse. gpo_sth_stt_mult [1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. ddh gpo_sth_stt[4:0] 4: 0 sth pulse start position. gpo_sth_width 7: 0 default : 0x01 access : r/w - 7:6 reserved. gpo_sth_width_ mult[1:0] 5: 4 00: x1. 01: x4. 10: x8. 11: x16. deh gpo_sth_width [3:0] 3: 0 sth pulse width. gpo_oeh_stt 7: 0 default : 0xa3 access : r/w out_inv 7 output inverse. gpo_oeh_stt_mult [1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. dfh gpo_oeh_ stt[4:0] 4:0 oeh pulse start position. gpo_oeh_width 7: 0 default : 0x0b access : r/w - 7:6 reserved. gpo_oeh_width_ mult[1:0] 5: 4 00: x1. 01: x4. 10: x8. 11: x16. e0h gpo_oeh_width [3:0] 3:0 oeh pulse width. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 88 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description gpo_ oev _stt 7: 0 default : 0x01 access : r/w out_inv 7 output inverse. gpo_oev_stt_mmult [1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. e1h gpo_oev_stt[1:0] 4:0 oev pulse start. gpo_oev_width 7: 0 default : 0x6d access : r/w - 7:6 reserved. gpo_oev_width_ mult[1:0] 5: 4 00: x1. 01: x4. 10: x8. 11: x16. e2h gpo_oev_width [3:0] 3:0 oev pulse width. gpo_ckv_stt 7: 0 default : 0x2d access : r/w out_inv 7 output inverse. ckv_stt_ mult[1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. e3h gpo_ ckv_stt[4:0] 4:0 ckv pulse start. gpo_ckv_stt 2 7: 0 default : 0x04 access : r/w - 7:6 reserved. ckv_stt2_mult [1:0] 5: 4 00: x1. 01: x4. 10: x8. 11: x16. e4h gpo_ ckv_st2[3:0] 3:0 ckv pulse start 2. gpo_ckv_width 7: 0 default : 0x5f access : r/w - 7 reserved. ckv_width_ mult[1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. e5h gpo_ ckv_width[4:0] 4:0 ckv pulse width. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 89 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description gpo_stv_ln_th 7: 0 default : 0x46 access : r/w - 7 reserved. gpo_stv_1ln 6 s tv width is 1 line. e6h gpo_ stv _line_t h 5: 0 stv line position gpo_ stv _stt 7: 0 default : 0x29 access : r/w out_inv 7 output inverse. stv_stt_mult[1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. e7h gpo_ stv_stt[4:0] 4: 0 stv pulse start. gpo_stv_ width 7: 0 default : 0x00 access : r/w - 7:6 reserved. stv_width_mult [1:0] 5: 4 00: x1. 01: x4. 10: x8. 11: x16. e8h gpo_stv_width [3:0] 3: 0 stv pulse width. gpo_oev2_stt 7: 0 default : 0x04 access : r/w out_inv 7 output inverse. oev2_stt_mult [1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. e9h gpo_oev2_stt[4:0] 4:0 oev2 pulse start. gpo_oev3_stt 7: 0 default : 0x04 access : r/w out_inv 7 output inverse. oev3_stt_mult [1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. eah gpo_oev3_stt[4:0] 4:0 oev3 pulse start. hstt_dly_l 7: 0 default :0x04 access : r/w ebh hstt_dly[7:0] 7: 0 h start delay numbers low byte. ech hstt_dly_h 7: 0 default :0xa4 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 90 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description ext_dis_rng 7:4 extraction start point in line extraction mode. - 3 reserved. hstt_dly_en 2 h start delay enable. hsst_dly[9:8] 1: 0 h start delay numbers high byte. clk_dly_syncout 7: 0 default : 0x00 access : r/w frpseth 7 set high to invert rgb data when frp disable (bk1_d2[1]=1). - 6 reserved. tc_gpio_sel 5 0 : tc function. 1: gpio function. oev_md_sel 4 0 : normal mode. 1: special mode. edh clk_dly_sel_tc [3:0] 3:0 tcclk delay select. gpo_ckv_end 2 7: 0 default : 0x28 access : r/w ckv2_en 7 ckv2 enable. ckv_end2_mult[1:0] 6: 5 00: x1. 01: x4. 10: x8. 11: x16. eeh gpo_ckv_end 2 4:0 ckv2 end point. q1h_settin g 7: 0 default : 0x08 access : r/w q1h_enable 7 q1h output from seq_mode pin, toggle point is using oev3 signal start point. tcclk_inv_mode 6: 3 0001: tcclk invert every field. 0011: tcclk invert when q1h is high. 0101: tcclk invert when q1h and field are high. 1001: tcclk invert when q1h is low and field is high. - 2 reserved. intout_oen 1 testmode. pad_intout output enable control. 0: output. 1: input. efh clkin_sel 0 testmode external clock select. 0: pad_intout. 1: pad_clkin. wdt0 7: 0 default : 0x00 access : r/w f0h wdt_testmd 7 csog test mode for wdt counter. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 91 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description wdt_ld 6 watch dog timer load value by sw. wdt_en 5 watch dog timer enable bit. - 4:0 reserved. wdt1 7: 0 default : 0x00 access : r/w f1h wdt_width 7:0 watch dog timer width. wrlock0 7: 0 default : 0x00 access : r/w wrlock0 7 register lock (work with wrlock1). register access is disabled when wrlock0 and wrlock1 are high. register access is enabled when wrlock0 and wrlock1 are low. f2h - 6:0 reserved. pwmclk 7: 0 default : 0x00 access : r/w db_en 7 double buffer enable. 0: disable. 1: enable. p2ren 6 pwm2 reset every frame enable. 0: disable. 1: enable. p1ren 5 pwm1 reset every frame enable. 0: disable. 1: enable. p2pol 4 pwm 2 polarity when enhance pwm2 enable. ep2en 3 enhance pwm2 enable. 0: disable. 1: enable. p1pol 2 pwm1 polarity when enhance pwm1 enable. ep1en 1 enhance pwm1 enable. 0: disable. 1: enable. f3h pclk 0 pwm1/2 base clock select. 0: 14.318mhz. 1: 14.318mhz / 4. pwm1c 7: 0 default : 0x00 access : r/w pwm1_pol 7 pwm1 polarity. f4h pwm1_ctun[6:0] 6:0 pwm1 coarse adjustment. f5h pwm2c 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 92 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. analog register (bank = 01) index name bits description pwm2_pol 7 pwm2 polarity. pwm2_ctun[6:0] 6:0 pwm2 coarse adjustment. pwm1epl 7: 0 default : 0x00 access : r/w f6h epwm1p[7:0] 7:0 enhance pwm1 period. pwm1eph 7: 0 default : 0x00 access : r/w f7h epwm1p[15:8] 7:0 enhance pwm1 period. pwm2epl 7: 0 default : 0x00 access : r/w f8h epwm2p[7:0] 7:0 enhance pwm2 period. pwm2eph 7: 0 default : 0x00 access : r/w f9h epwm2p[15:8] 7:0 enhance pwm2 period. pwm5l 7: 0 default : 0x00 access : r/w fah pwm5[7:0] 7:0 pwm5 period. pwm5h 7: 0 default : 0x00 access : r/w - 7:5 reserved. fbh pwm5[12:8] 4:0 pwm5 period. pwm6l 7: 0 default : 0x00 access : r/w fch pwm6[7:0] 7:0 pwm6 period. pwm6h 7: 0 default : 0x00 access : r/w - 7:5 reserved. fdh pwm6[12:8] 4:0 pwm6 period. - 7: 0 default : - access : - feh ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 93 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) video decoder register (bank = 02) index name bits description status1 7: 0 default : - access : ro 01h readbus1 7:0 test bus 1. status2 7:0 default : - access : ro 02h readbus2 7:0 test bus 2. status3 7:0 default : - access : ro 03h readbus3 7:0 test bus 3. status_mux 7:0 default : 0x00 access : r/w 04h readbus_ctrl 7: 0 viptestmux address control of readbus1, readbus2, and readbus3. - 7: 0 default : - access : - 05h ~ 06h - 7:0 reserved. dsp_add_prt 7: 0 default : 0x00 access : r/w 07h dsp_add_prt[7:0] 7:0 dsp register address port. dsp_wdat_prt 7: 0 default : 0x00 access : r/w 08h dsp_wdat_prt[7:0] 7:0 dsp register write data port. dsp_rdat_prt 7: 0 default : - access : ro 09h dsp_rdat_prt[7:0] 7:0 dsp register read data port. - 7: 0 default : - access : - 10h - 7:0 reserved. comb_ll_en 7: 0 default : 0x00 access : r/w - 7:1 reserved. 11h apl_comb_ll_e n 0 1: mux to select com line lock mode. - 7: 0 default : - access : - 12h ~ 13h - 7:0 reserved. soft_rst 7: 0 default : 0x10 access : r/w soft_rst 7 1 : softrest afec modules. 14h - 6:0 reserved. fpga_ctrl 7: 0 default : 0xa8 access : r/w 15h fpga_ctrl 7:0 reserved for fpga control. reg_soft_rst 2 7: 0 default : 0x00 access : r/w 16h reg_soft_rst 2 7:0 reserved for hw testing. 17h clk_ctrl 7: 0 default : 0xc9 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 94 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description fscpll_mode 7 0 : external fsc clock mode. 1: internal fsc clock mode. adc_double 6 adc double sample rate option. reg_clk_vd_vip 5: 4 00: 4 fsc clock on digital. 11: 8 fsc clock on digital. reg_vco_type 3: 2 10: vco 16 fsc. 01: vco 8 fsc. 00: vco 4 fsc. reg_adc_clk_la g 1:0 clk_cc / clk_adc phase diff. cstate_ctrl 7: 0 default : 0x86 access : r/w ctrl_md 7:5 default: 100b, auto control mode. - 4 reserved. 18h ctrl_state 3: 0 state stable state value; default: 0110b. mvdet_en 7: 0 default : 0xc0 access : r/w mv_detec_en 7 microvision detect enable. 0: disable. 1: enable. - 6:5 reserved. dsp_sync_alw 4 allow dsp to control sync_found. dsp_apl_alw 3: 2 0: allow dsp to control apl_freq_ideal (center frequency). 19h secam_md 1: 0 1: allow dsp to control apl_freq and apl_phs (full frequency/phs control). svd_en 7: 0 default : 0x40 access : r/w svideo_en 7 0 : chroma source from cvbs-channel input. 1: chroma source from c-channel input. adc_c_alwy_o n 6 chroma adc 16fsc-to-4fsc down-sampling is enabled. 1ah clamdsm_ctrl[15:10] 5:0 clamping 12-bit control code; integer parts. bklvl_force 1 7: 0 default : 0x80 access : r/w disclamp3 7 h w clamping frozen 3 times if sync magnitude is small. clmp_frez_zero 6 h w clamping set to zero when frozen. 1bh clamdsm_ctrl[9:4] 5:0 clamping 12-bit control code; fractional parts. bklvl_force 2 7: 0 default : 0xff access : r/w 1ch clmfze_vrge 7:0 clamp freeze of v range. vcr_vlsht 7: 0 default : 0xff access : r/w 1dh clmfze_hrge 7:0 clamp freeze of h range. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 95 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description dsp_en 7: 0 default : 0x80 access : r/w dsp_en_sys 7 1 : enable sw dsp function. 1eh - 6:0 reserved. clmp_c_en 7: 0 default : 0x60 access : r/w clmp_c_en 7 2 nd adc chroma clamping enable. 1fh clmp_k1_ini 6: 0 hw clamping k1 when system not stable. apll_ctrl1 7: 0 default : 0xbc access : r/w apl_en 7 analog burst-lock pll enable. apl_type 6:4 apl type. - 3:2 reserved. apl_en2 1 n o state 7, when no bust. 20h clmp_6b_force 0 clamp value 6-bit test mode enable. apll_ctrl2 7: 0 default : 0x18 access : r/w clmp_2dsm 7 se cond order clamp method. apl_comb_ll_tst[1] 6 0 : comb-line-lock disabled if vcr. 1: com-line-lock enabled even for vcr. apl_comb_ll_tst[0] 5 0 : fractional sync phase is used. 1: integer pd from comb. dpl_phs_cal 4 dpl phase calibration. apl_cezanne 3 for cezanne fpga test. palswh_mode 2:1 pal switch mode control. 21h apl_comb_ll_e n 0 comb line-locked mode enable. apl_freq_m d 7: 0 default : 0x61 access : r/w apl_freq_md[7:5] 7:5 apl freq mode. - 4:3 reserved. 22h aclpz_wdth 2:0 clamping width. apll_tran ge 7: 0 default : 0x40 access : r/w apl_freq_lmt 7:5 burst pll frequency limitation. 0: 125ppm. 2: 250ppm. 4: 500ppm. 6: 1000ppm. - 4:1 reserved. 23h apl_k_force 0 apl k value force enable. 24h apl_k1_noisy 7: 0 default : 0x04 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 96 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description apl_k1_noisy[7:0] 7:0 apll phase tracking coefficients for noisy broadcast. apl_k2_noisy 7: 0 default : 0x02 access : r/w 25h apl_k2_noisy[7:0] 7:0 apll frequency tracking coefficients for noisy broadcast. apl_k1_norm 7: 0 default : 0x10 access : r/w 26h apl_k1 7:0 apll phase tracking coefficients for normal condition. apl_k2_norm 7: 0 default : 0x08 access : r/w 27h apl_k2 7:0 apll frequency tracking coefficients for normal condition. apl_k1_vcr 7: 0 default : 0x02 access : r/w 28h apl_k1_vcr 7:0 apll phase tracking coefficients for vcr. apl_k2_vcr 7: 0 default : 0x01 access : r/w 29h apl_k2_vcr 7:0 apll frequency tracking coefficients for vcr. mode_pfsc 7: 0 default : 0x20 access : r/w md_pfsc[7] 7 0 : auto fsc. 1: manual fsc. md_pfsc[6:4] 6:4 when bit[7]=1, 000: fsc=4.43361875 mhz. 001: fsc=4.406 mhz. 010: fsc=3.579545 mhz. 100: fsc=3.57561149 mhz. 110: fsc=3.58205625 mhz. vdfd_aswfsc 3 internal blind fsc try. vdfd_aswfsc1 2 internal blind fsc try1. halfwin_op 1 h alf window period option. 0: asserted between 1/4 to 3/4 line period. 1: asserted between 1/2 to 1 line period. 2ah oeinv_md 0 odd_even_invert bit inversion mode. 0: directly bypass. 1: inverse. vdfd_ctrl1 7: 0 default : 0x7e access : r/w vdfd_fd_l 7:4 fast attack frequency tracking time period. 2bh vdfd_phsstd_l 3:0 monitor phase tracking time period. vdfd_ctrl2 7: 0 default : 0x67 access : r/w phs_diff_thrd 7:4 phase tracking deviation large threshold. 2ch phs_std_range 3:0 phase tracking deviation small threshold. 2d h fd_k 7: 0 default : 0xc0 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 97 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description fd_k 7:4 fast attack frequency tracking coefficient. apl_phs_ofst[11:8] 3:0 preferred phase offset of the analog burst-locked pll. apl_phs_ofst 7: 0 default : 0x00 access : r/w 2eh apl_phs_ofst[7:0] 7:0 preferred phase offset of the analog burst-locked pll. black_sel 7: 0 default : 0x24 access : r/w setup_yes 7: 5 0x: based on confirm mode auto determine. ntsc: setup. pal: no setup. 10: force no setup for ntsc. 11: force setup for pal. - 4:2 reserved. 2fh - 1:0 reserved. clamp_ctrl 7: 0 default : 0x01 access : r/w clampdac_ctrl[7:6] 7: 6 00: auto clamping control. 01: auto clamping control, but polarity inverted. 10: force clamping control by bit[5:0]. 11: auto clamping control. 30h clampdac_ctrl[5:0] 5:0 clamping control value. clamp_coef 1 7: 0 default : 0x40 access : r/w clmp_type_st3bot 7 clmp_bot function enable in stae3. 31h clmp_k1 6:0 clamping speed; the larger the faster. 7 b101_1000 suggested for 1.00 uf. 7 b100_0000 suggested for 0.10 uf. (default) 7 b010_1000 suggested for 0.01 uf. clamp_coef 2 7: 0 default : 0xa0 access : r/w clmp_type 7 back-porch clamping enable (default =1). 32h clmp_k2 6:0 leakage current tracking speed. smaller value is preferred. 7'b001_0000 suggested for 1.00 uf. 7'b010_0000 suggested for 0.10 uf. (default). 7'b011_0000 suggested for 0.01 uf. clamp_coef 3 7: 0 default : 0x00 access : r/w clmp_lkg_mode 7:4 leakage control mode. 33h adcloss_cnt 3:0 count value of adc loss status. clamp_coef 4 7: 0 default : 0x82 access : r/w clmp_botspd 7:6 bottom reference lpf selection. 34h clmp_dlkg_mac 5:0 delta leakage is bounded by +- (clamp_dlkg_max/512). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 98 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description clamp_ref_sel 1 7: 0 default : 0x0a access : r/w blanklvl_ctrl 7 blank level control. blank_lvl[8] 6 blank level bit[8]. 35h clmp_lkg 5:0 if clamp_lkg_md = 1011, leakage is forced by clamp_lkg[4:0] * sign; where, sign=+1 if bit[5]=1, and sign=-1 if bit[5]=0. default: 6 d10. clamp_coef 5 7: 0 default : 0x45 access : r/w clmp_botsel 7:5 clamp bot selection enable. 36h clmp_err_max 4:0 back porch level error for clamping is bounded by +- clmp_err_max*8 (default: 5 d25). clamp_ref_sel 2 7: 0 default : 0xf0 access : r/w 37h blank_lvl[7:0] 7:0 blank level. vstrobe_limit 7: 0 default : 0x13 access : r/w blacklvl_ctrl 7 black level control. black_lvl[8] 6 black level bit[8]. hv_vcntsel 5 1 : enable 2 nd integration protection for v extraction. hv_vlinprot 4 0 : enable next v extraction after 50 lines. 1: enable next v extraction after 200 lines. botav_insel 3 bottom of active video input selection. 38h bot_insel 2:0 bottom of whole line input selection. vstrobe_protect 7: 0 default : 0x6c access : r/w wp_insel 7: 5 sync input lpf bw selection. hv_insel 4: 2 hsync/vsync slicer level selection. 39h top_insel 1:0 top level input selection. black_lvl 7: 0 default : 0xcc access : r/w 3ah black_lvl[7:0] 7:0 black level value. hv_vexth 7: 0 default : 0x7d access : r/w 3bh hv_vexth 7: 0 0: v extract by line length unit. 1: v extract by manual pixel length units. hv_c trl1 7: 0 default : 0x2a access : r/w 3ch hv_vsel 7: 6 00: v extract native. 01: v extrat native synchronize to next line start/middle. other reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 99 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description hv_vthrdsel 5: 4 00: 3/8 line. 01: 6/8 line. 10: 1.25 line. 11: 1.75 line. as threshold for v extract. hv_intcnt 3:0 composite sync pixel lengths filter for v extract. v_postcoast 7: 0 default : 0x00 access : r/w vcost_fext 7:6 coast forward control. 3dh vcost_bext 5:0 coast backward control. hv_slictrl 7: 0 default : 0x0c access : r/w 3eh hv_slictrl 7: 0 hsync/vsync slicer control. hv_hsliofsthys 7: 0 default : 0xc0 access : r/w hv_hsliofsth ys 7: 4 hsync slicer line offset. 3fh agc_fine_lsb 3:0 agc fine gain (lower 4 bits). pga_ctrl1 7: 0 default : 0xc1 access : r/w pga_auto 7 0 : manual pga set by agc_coarse[1:0]. 1: auto pga switch. pga_fswt 6 0 : pga switch in vsync. 1: pga switch in hsync. agc_coarse 5: 4 00: pga x 1. 01: pga x 2. frez_clmpdisb k 3 freeze clamp function; vsync selection. 40h sync_mag_low_th 2:0 if sync magnitude is low, freeze hw clamping 3 times. pgh_top_th 7: 0 default : 0xda access : r/w 41h pga_th_top 7:0 if agc_fine[11:0]>=16*pga_th_top[7:0], use smaller pga and 16*pga_h2l[7:0]. pga_bot_th 7: 0 default : 0x40 access : r/w 42h pga_th_bot 7:0 if agc_fine[11:0]<=16*pga_th_bot[7:0], use larger pga and 16*pga_l2h[7:0]. agc_ctrl1 7: 0 default : 0x14 access : r/w 43h - 7 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 100 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description agc_md 6: 5 00: auto, reg_agc_k used for both search and lock. 01: auto, reg_agc_k used for search, clipping delta-gain=-1, 0, +1 for lock. 10: freeze gain. 11: load gain=agc_fine*16. default=1. agc_lock_ctrl 4 agc lock control. agc_type 3: 2 00: sync. 01: sync. 10: color bust. 11: hybrid of 1 and 2. default=1, hsync as primary reference, color burst is for acc. agc_lowth_pga 1:0 during pga switching, pga must be larger than agc_lowth_pga. agc_fine 7: 0 default : 0xc0 access : r/w 44h agc_fine 7: 0 used when agc_mode=11. agc_ctrl2 7: 0 default : 0x42 access : r/w agc_avgl 7:5 agc average lines=2^( agc_avgl + 1). - 4 reserved. agc_waitl 3:1 lines to wait for analog settling down=2^( agc_waitl) after each gain update. 45h - 0 reserved. agc_k_ctrl 7: 0 default : 0x73 access : r/w agc_k_fast 7:4 fast-attack agc update speed. delta_gain=+-(agc_k_fast*4+3)/256*gain_true. 46h agc_k 3: 0 sync magnitude agc update speed. delta_gain=amp_err/256*(1+ agc_k)/32*gan_true. agc_ctrl3 7: 0 default : 0x3f access : r/w agc_bklclip 7:5 agc black level clip enable. 47h agc_clip 4:0 the sync magnitude error for agc is bounded by +-4*reg_agc_clip. pga_swtich_th 1 7: 0 default : 0xc0 access : r/w 48h pga_l2h 7: 0 used when agc_fine<=pga_th_bot*16. default: 3072/16=8 d192. pga_swch_th 2 7: 0 default : access : r/w 49h pga_h2l 7: 0 used when agc_fine<=pga_th_bot*16. default: 1238/16 = 8'd64. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 101 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description agc_lowth 7: 0 default : 0xa0 access : r/w 4ah agc_lowth 7:0 when pga=agc_lowth_pga, agc_fine[11:0] must be smaller than 16*agc_lowth. pga_ofst 7: 0 default : 0x40 access : r/w 4bh pga_ofst 7:0 adc vref offset=vref_min/(vref_max-vref_min)*4096/16. brst_windo w1 7: 0 default : 0x62 access : r/w brst_mask_0 7: 5 hsync trailing edge trasition region maskout for burst calculation. 4ch brst_beg 4:0 burst window beginning position; move to sw. brst_windo w2 7: 0 default : 0x40 access : r/w 4dh brst_end 7:0 burst window end position; move to sw. bk_window 1 7: 0 default : 0x05 access : r/w bkprh_ctr[8] 7 back-porch window center position. bkprh_sel 6 back-porch selection. bkprh_autsw 5:4 back-porch auto switch. 4eh bkprh_win 3:0 back-porch window width=(*4+4). bk_window 2 7: 0 default : 0x68 access : r/w 4fh bkprh_ctr[7:0] 7:0 back-porch window center position. brst_th 7: 0 default : 0x80 access : r/w brst_thrd 7:4 burst threshold. 50h brst_amp_thrd 3:0 burst found amplitude threshold. brstmag_ctrl 7: 0 default : 0x38 access : r/w brstmag_ctrl 7 burst magnitude control. 51h brst_mag[8:2] 6:0 burst magnitude value. comb_ll_ctrl 7: 0 default : 0x04 access : r/w brst_mag[1:0] 7:6 burst magnitude value. - 5:4 reserved. pal_blind_pd_e n 3 ntsc; 180 degree phase detection enable. brst_phs_chk_mag 2 burst phase of the current line is ignored if brst_mag MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 102 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description - 4:3 reserved. fsc_tst_try[2] 2 fsc selection 1.25*fsc and 0.8*fsc bpf magnitude type. fsc_tst_try[1] 1 fsc selection 1.0*fsc bpf magnitude type. fsc_tst_try[0] 0 fsc selection bpf magnitude snapshop taken at the end of the burst window. color_off 7: 0 default : 0x08 access : r/w kill_cspout 7: 6 00 or 01: auto color kill. 10: force show color. 11: force kill color. - 5 reserved. 55h pal_lines_th 4:0 lines for pal/ntsc detection=64 * pal_lines_th. fsc443/357 dect1 7: 0 default : 0x18 access : r/w - 7:6 reserved. 56h fsc_thrd1_pa ss 5:0 fsc threshold1 pass. fsc443/357 dect2 7: 0 default : 0x28 access : r/w - 7:6 reserved. 57h fsc_thrd1_fail 5:0 fsc threshold1 fail. fsc443/357 dect3 7: 0 default : 0x10 access : r/w - 7:6 reserved. 58h fsc_thrd0_pa ss 5:0 fsc threshold0 pass. fsc443/357 dect4 7: 0 default : 0x20 access : r/w - 7:6 reserved. 59h fsc_thrd0_fail 5:0 fsc threshold0 fail. brst_unknow_th 7: 0 default : 0x10 access : r/w - 7 reserved. fsc_tst_ma sk 6: 4 hsync trailing edge trasition region maskout for fsc selection filters. 5ah fsc_thrd_no_brst 3:0 fsc threshold for no burst detection. fsc443/357 dect5 7: 0 default : 0x98 access : r/w fsc_thrd_mag_hyst[ 3:2] 7:6 fsc threshold magnitude of hsync start. 5bh fsc_thrd_mag_443 5:0 fsc threshold magnitude of 4.43 mhz. fsc443/357 dect6 7: 0 default : 0x98 access : r/w 5ch fsc_thrd_mag_hyst[ 1:0] 7:6 fsc threshold magnitude of hsync start. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 103 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description fsc_thrd_mag_358 5:0 fsc threshold magnitude of 3.58 mhz. acc_ctrl 7: 0 default : 0x08 access : r/w acc_ctrl 7:6 auto chroma control. 01: reset chroma_gain=1. 11: load chroma_gain=acc_gain[13:0]/64. 5dh acc_gain[5:0] 5:0 auto-chroma-control gain. acc_gain 7: 0 default : 0x20 access : r/w 5eh acc_gain[13:6] 7:0 auto-chroma-control gain. agc_delta 7: 0 default : 0x28 access : r/w agc_delta[7:5] 7:5 agc delta value. wp_sim_spd 4:3 wp simulation speedup. 5fh wp_lvl_spd 2:0 wp level speedup. wp_ctrl1 7: 0 default : 0x15 access : r/w acc_c_peak_lpf 7:6 chroma peak detection update speed. 00: slow, narrow-band-width. 11: fast, wide-band-width. - 5 reserved. wp_th[8] 4 desired white level=512+reg_wp_th. 60h agc_k_wp 3:0 white peaking agc update speed. delta_gain=white_err/256*(1+reg_agc_k)/ 32*gain_true. wp_thrd 7: 0 default : 0x24 access : r/w 61h wp_thrd[7:0] 7:0 white peak threshold value. ap_synthrd2reag c 7: 0 default : 0x78 access : r/w 62h wp_synthrd2reagc 7:0 wp sync threshold of agc. - 7: 0 default : - access : - 63h ~ 64h - 7:0 reserved. agc_ctrl4 7: 0 default : 0x55 access : r/w - 7:2 reserved. 65h wp_waitth 1: 0 number of sync-mag agc operations before wp mode. 00: 255 operations. 01: 127 operations. 10: 63 operations. 11: 31 operations. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 104 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description wp_ctrl2 7: 0 default : 0x70 access : r/w wp_mode 7: 5 0xx: internally automatic white-peaking control. 100: disable white-peaking. 101: hold sync magnitude agc if white level is too high. 110: reserved. 111: normal white-peaking agc. wp_montr_spd 4:2 wp monitor speed. 66h adcovsle_thrd 1:0 wp threshold selection. wp_redo 7: 0 default : 0x17 access : r/w round_ctrl 7:5 afec signal rounding selection. remov_hf_noise 4 enable 13-tap cvbs low-pass filter to remove high-frequency noise. round_ctrl[3:2] 3: 2 7-tap chroma-trap filter, cctrap, rounding. 00: truncate. 01: round. 10: dither. round_ctrl[1] 1 afec self-test 1d luminance rounding. 0: truncate. 1: round. 67h round_ctrl[0] 0 afec self-test 1d chroma rounding. 0: truncate. 1: round. clk_ctrl1 7: 0 default : 0x45 access : r/w adc_84_round 7:6 round control for 8fsc-to-4fsc downsampling. 0: truncate. 1: round. dac_latch_i nv 5 option for datalatch from 4fsc to 8fsc. 3dac_en 4 enable afec data output to dac. filsel 3:2 filter selection. 68h adc_168_round 1:0 round control for 16fsc-to-8fsc downsampling. 0: truncate. 1: round. src_ctrl1 7: 0 default : 0x00 access : r/w selyc 7 0 : yc source from afec for testing purpose. 1: yc source from comb for display. - 6:5 reserved. 69h bypass_y 4 bypass cvbs source for testing purpose. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 105 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description comb601h_sync 3 1 : use the hs444 as the mvda_hs output. comb601v_sync 2 1 : use the vs444 as the mvda_vs output. comb601f_sync 1 1 : use the fld444 as the mvda_f output. combpass_sync 0 1 : the hs444 and vs444 as the bypass sync. 0: afec_hs and afec_vs as the bypass sync output. vcr_detect 1 7: 0 default : 0x51 access : r/w vcr_mode 7: 6 vcr mode enable. vcr_hd_dly 5: 4 vcr head switch number. - 3 reserved. 6ah vs_stb 2: 0 vs strobe. vcr_detect 2 7: 0 default : 0xaa access : r/w vcr_ldt 7: 4 vcr line margin. fast_vt_det 3 fast vertical line detection. 6bh vcr_thrd 2: 0 vcr threshold. vcr_precoast 7: 0 default : 0xf0 access : r/w vcr_precoast 7:4 pre-coast value for vcr mode. hv_hslisel_vcr 3: 2 hsync slicer selection for vcr mode. 6ch hv_slilow_sel 1: 0 hsync/vsync slicer low selection. - 7: 0 default : - access : - 6dh - 7:0 reserved. vcr_vlset 7: 0 default : 0x14 access : r/w 6eh vcr_vlset 7:0 pac/ntsc vline tunning. 7: 0 default : access : rst_afec_sel 7 0 : partial reset afec. 1: global reset afec. - 6:4 reserved. dpl_dde_en 3 dpl double de enable. dde_en 2 double de enable. dpl_hs_en 1 dpl hs enable. 6fh dpl_de_en 0 dpl de enable. ini_ctrl1 7: 0 default : 0x84 access : r/w fstagc_en 7 fast agc mode. - 6 reserved. 70h clmp_botmd 5:4 clamp on bottom mode. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 106 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description adsmal_thrd 3:0 threshold for detecting small aoc swing. botref_lvl 7: 0 default : 0xa0 access : r/w 71h botref_lvl 7:0 bottom reference level. hv_slc_ctrl 7: 0 default : 0x37 access : r/w hv_slcfze 7: 6 hsync/vsync slice freeze control. hv_slcdif 5: 4 hsync/vsync slice difference. 72h hv_slcdlt 3: 0 hsync/vsync slice limit. ini_ctrl1 7: 0 default : 0x52 access : r/w hv_vslisel 7: 6 00: 2/8 syn_magnitude as hslice level. 01: 4/8 syn_magnitude as hslice level. 10: 5/8 syn_magnitude as hslice level. 11: 6/8 syn_magnitude as hslice level. hv_hslisel 5: 4 00: 2/8 syn_magnitude as vslice level. 01: 4/8 syn_magnitude as vslice level. 10: 5/8 syn_magnitude as vslice level. 11: 6/8 syn_magnitude as vslice level. 73h 656_hdes_vcr_ofst 3: 0 656 sav position offset when vcr. slice_mux 7: 0 default : 0x97 access : r/w 74h slice_mux 7: 0 slicer level selection. 656_ofst 7: 0 default : 0x40 access : r/w - 7 reserved. 75h 656_ofst 6: 0 56 sav position offset in vcr mode. 656_ctrl1 7: 0 default : 0x02 access : r/w - 7:5 reserved. dbclk_test 4 clock testing. - 3 reserved. 656_blnk_md 2 656 blank mode. 656_en 1 enable 656 mode. 76h abnml_chk 0 abnormal check enable. 656_blnk_max 7: 0 default : 0x02 access : r/w 77h 656_blnk_max[7:0] 7: 0 656 blink max value. yuv 7: 0 default : 0x00 access : r/w 78h yuv[7:0] 7: 0 used as input of the 4fsc-to-16fsc up-sampling if selups=3. 79h 656_hdes1 7: 0 default : 0x18 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 107 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description 656_hdes_o[9:2] 7: 0 sda start position. (656_hdesm, 656_hdesl) itu656 sav position. for vcr, 656_hdes=656_hdes_o-656_hdes_vcr_ofst*4. otherwise, 656_hdes=656_hdes_o. 656_hdes2 7: 0 default : 0x20 access : r/w 656_hdes_o[1:0] 7:6 itu656 sav position. - 5:2 reserved. 656_inv_f 1 656 field inverse. 7ah - 0 reserved. 656_hdew 7: 0 default : 0xb3 access : r/w 7bh 656_hdew 7:0 itu656 active data width (*8+7). slmis_ctrl 7: 0 default : 0xc0 access : r/w 7ch slmis_ctrl[7:0] 7:0 enable slice miss freeze. noise_mlin e 7: 0 default : 0x04 access : r/w 7dh noise_mline 7:0 move noise level during specify line number. 656_ctrl2 7: 0 default : 0x80 access : r/w 656_clkinv 7 use d for fpga testing. 656_clkdly 6: 5 used for fpga testing. 656_lstsel 4 use d for fpga testing. 656_test 3: 2 used for fpga testing. 7eh test_mode 1: 0 used for fpga testing. 444_vd_ctrl 7: 0 default : 0x62 access : r/w seldac 7: 6 source for 3 dacs. 00: comb. 01: afec test mode. 10: 444. 11: upsampling source. 3dac_inshv 5 insert hv into display dac source. 3dac_hsel 4 insert h s source selection. 0: window pll. 1: display pll. 3dac_insblac k 3 insert black level back to dac source. 7fh reg_selfb 2 0 : ycbcr source from afec test mode. 1: ycbcr source from comb444. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 108 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description reg_selups 1: 0 upsampling source. 10: test mode 444. 11: comb ycbcr 444. nco_fsc0 7: 0 default : 0x48 access : r/w 80h fsc_nco0[23:16] 7:0 {nco_fsc0} 4.43 mhz synthesis clock. frequency synthesizer 4*fsc for 4.43361875 mhz. (for reg_fsc_table[4]=0.) syncthesis-base/(4*fsc)*2^22/8. nco_fsc0 7: 0 default : 0x2d access : r/w 81h fsc_nco0[15:8] 7:0 {nco_fsc0} 4.43 mhz synthesis clock. nco_fsc0 7: 0 default : 0x01 access : r/w 82h fsc_nco0[7:0] 7:0 {nco_fsc0} 4.43 mhz synthesis clock. nco_fsc1 7: 0 default : 0x59 access : r/w 83h fsc_nco1[23:16] 7:0 frequency synthesizer 4*fsc for 3.57954545 mhz (for fsc_table[4]=0). nco_fsc1 7: 0 default : 0x65 access : r/w 84h fsc_nco1[15:8] 7:0 {nco_fsc1} 3.579 mhz synthesis clock. nco_fsc1 7: 0 default : 0x97 access : r/w 85h fsc_nco1[7:0] 7:0 {nco_fsc1} 3.579 mhz synthesis clock. nco_fsc2 7: 0 default : 0x59 access : r/w 86h fsc_nco2[23:16] 7:0 frequency syncthesizer 4*fsc for 3.57561149 mhz (for fsc_table[4] =0). nco_fsc2 7: 0 default : 0x7e access : r/w 87h fsc_nco2[15:8] 7:0 {nco_fsc2} 3.582 mhz synthesis clock. nco_fsc2 7: 0 default : 0x74 access : r/w 88h fsc_nco2[7:0] 7:0 {nco_fsc2} 3.582 mhz synthesis clock. nco_fsc3 7: 0 default : 0x59 access : r/w 89h fsc_nco3[23:16] 7:0 frequency sunthesizer 4*fsc for 3.58205625 mhz (for fsc_table[4] = 0). nco_fsc3 7: 0 default : 0x55 access : r/w 8ah fsc_nco3[15:8] 7:0 {nco_fsc3} 3.576 mhz synthesis clock. nco_fsc3 7: 0 default : 0x8b access : r/w 8bh fsc_nco3[7:0] 7:0 {nco_fsc3} 3.576 mhz synthesis clock. 8ch reg_fsc_nco 4 7: 0 default : 0x4a access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 109 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description fsc_nco4[23:16] 7:0 requency synthesizer 4*fsc for 4.28515625 mhz (for reg_fsc_table[4] = 0). fsc_nco4 7: 0 default : 0xad access : r/w 8dh fsc_nco4[15:8] 7:0 requency synthesizer 4*fsc for 4.28515625 mhz (for reg_fsc_table[4] = 0). fsc_nco4 7: 0 default : 0x27 access : r/w 8eh fsc_nco4[7:0] 7:0 requency synthesizer 4*fsc for 4.28515625 mhz (for reg_fsc_table[4] = 0). fsc_table 7: 0 default : 0x00 access : r/w - 7:5 reserved. fsc_table[4] 4 frequency synthesizer control. 0: fsc_nco0, 1, 2, 3, and 4 are used. 1: specified by fsc_table[3:2]. fsc_table[3:2] 3:2 frequency synthesizer base. 00: 160mhz. 01: 15*14.31818mhz. 10: 216mhz. 11: 15*14.31818mhz. only valid for fsc_table[4] =1. 8fh fsc_table[1:0] 1:0 frequency synthesizer output. 00: 4*fsc. 01: 8*fsc. 10: 16*fsc. 11: 16*fsc. fsc_nco_err_443 7: 0 default : 0x00 access : r/w 90h fsc_nco_err_443 [15:8] 7:0 frequency synthesizer 4*fsc error for 4.43mhz; 2 s complement (auto scaled internally for 3.58mhz). fsc_nco_err_443 7: 0 default : 0x00 access : r/w 91h fsc_nco_err_443 [7:0] 7:0 frequency synthesizer 4*fsc error for 4.43mhz; 2 s complement (auto scaled internally for 3.58mhz). winiir_thrd_ctrl 7: 0 default : 0xa7 access : r/w winiir_thrd 1 7:4 iir window threshold 1. 92h winiir_thrd 0 3:0 iir window threshold 0. winfir_thrd_ctr l 7: 0 default : 0xa4 access : r/w winfir_thrd 1 7:4 iir window threshold 1. 93h winfir_thrd 0 3:0 iir window threshold 0. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 110 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description spl_spd_ctrl 1 7: 0 default : 0x14 access : r/w spl_spd_force 7:5 coarse hsync pll tracking speed. bit[2] forces using bit[1:0]. spl_spd=3: fastest. spl_spd=0: slowest. spl_spd_src h 4:3 coarse hsync pll tracking speed during hsync-search. spl_spd_clea n 2:1 coarse hsync pll tracking speed for clean signal. 94h - 0 reserved. spl_spd_ctrl 2 7: 0 default : 0x2a access : r/w spl_spd_nois y 7:6 coarse hsync pll tracking speed for noisy signal. spl_spd_vcr 5:4 coarse hsync pll phase tracking speed for vcr outside vsync. spl_spd_vcr _v 3:2 coarse hsync pll phase tracking speed for vcr during vsync. 95h spl_spd_vcr_pre 1:0 coarse hsync pll hsync-search lines. 00: 48. 01: 64. 10: 80. 11: 96. edges_noisy_thr d 7: 0 default : 0xa0 access : r/w noise_dc_sel 7: 6 noise magnitude estimation dc level selection. 00: iir_8. 01: iir_8. 10: cctrap_13. 11: cctrap. 96h edges_noisy 5:0 threshold of the average number of sliced edges per line to determine noisy mode (/ 4). edges_clean_thr d 7: 0 default : 0x05 access : r/w sync_inmux[2:1] 7: 6 slicer input pre-filter selection. 00: cctrap. 01: cctrap_13. 10: iir_8. 11: iir_16. sync_inmux[0] 5 s licer auxiliary pre-filter selection. 0: iir_8. 1: iir_16. 97h - 4 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 111 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description edges_clean 3:0 threshold of the average number of sliced edges per line to determine clean mode (/ 4). sync_win_ctrl1 7: 0 default : 0x43 access : r/w sync_inmux_vcr [2:0] 7: 5 hsync slicer input selection. - 4 reserved. 98h win_noisy 3:0 ciarse hsync pll pd limitaion window width for noisy mode (*8+7). sync_win_ctrl2 7: 0 default : 0x88 access : r/w sync_win 7:4 coarse hsync pll sync-lost detection window width (*4+4). 99h sync_win_src h 3:0 coarse hsync pll sync-found detection window width (*4+4). sync_ctrl1 7: 0 default : 0xf0 access : r/w sync_thrd_mi ss 7:4 coarse hsync pll sync search fail threshold. - 3:2 reserved. 9ah spl_srch_len g 1: 0 spl search length. sync_ctrl2 7: 0 default : 0x10 access : r/w - 7:6 reserved. 9bh sync_thrd 5:0 coarse hsync pll sync search pass (sync found) threshold (*4+3). sync_ctrl3 7: 0 default : 0x1c access : r/w - 7 reserved. 9ch sync_thrd_lost 6:0 coarse hsync pll sync sync-lost threshold (*16+15). dpl_nspl_high 7: 0 default : 0x6c access : r/w 9dh dpl_nspl[10:3] 7:0 pi-type display pll number of samples per line (msb); typically 864. dpl_nspl_lo w 7: 0 default : 0x00 access : r/w dpl_nspl[2:0] 7:5 pi-type display pll number of samples per line (lsb); typically 864. dpll_true8fsc 4 dpll under 8 fsc mode. 9eh - 3:0 reserved. spl_k2_vcr 7: 0 default : 0x40 access : r/w spl_k2_vcr 7:6 coarse hsync pll frequency tracking speed for vcr. 9fh spl_nspl_lmt 5:0 pi-type display pll frequency coasts if the coarse hsync pll deviation is larger than +/- 4*spl_nspl_lmt (try). a0h dpl_k1_forc e 7: 0 default : 0x20 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 112 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description dpl_k_force 7 force dpl k value. - 6 reserved. dpl_k1 5:0 pi-type display pll phase tracking coefficient k1. dpl_k2_forc e 7: 0 default : 0x60 access : r/w a1h dpl_k2 7:0 pi-type display pll frequency tracking coefficient k2. dpl_k1_noisy 7: 0 default : 0x10 access : r/w - 7:6 reserved. a2h dpl_k1_noisy 5:0 pi-type display pll phase tracking coefficient for noisy broadcast. dpl_k2_noisy 7: 0 default : 0x04 access : r/w a3h dpl_k2_noisy 7:0 pi-type display pll frequency tracking coefficient for noisy broadcast. dpl_k1_vcr 7: 0 default : 0x34 access : r/w - 7:6 reserved. a4h dpl_k1_vcr 5:0 pi-type display pll phase tracking coefficient for vcr. dpl_k2_vcr 7: 0 default : 0x6a access : r/w a5h dpl_k2_vcr 7:0 pi-type display pll frequency tracking coefficient for vcr. dpl_k1_vcr_v 7: 0 default : 0x34 access : r/w - 7:6 reserved. a6h dpl_k1_vcr_v 5:0 pi-type display pll phase tracking coefficient for vcr during vsync. dpl_k2_vcr 7: 0 default : 0x2c access : r/w - 7:6 reserved. dpl_vcr_fade_spd 5:4 pi-type display pll pd_max fading speed from vsync to active lines. 00: slow. 11: fast. a7h dpl_vcr_fade_start 3:0 pi-type display pll pe_max fading start lines (*2). dpl_k1_fast 7: 0 default : 0x30 access : r/w - 7:6 reserved. a8h dpl_k1_fast 5:0 pi-type display pll phase tracking coefficient for fast mode and initialization. dpl_k2_fast 7: 0 default : 0x65 access : r/w a9h dpl_k2_fast 7:0 pi-type display pll frequency tracking coefficient for fast mode and initialization. aah dpl_ctrl1 7: 0 default : 0x08 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 113 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description - 7:4 reserved. dpl_fast_line s 3:0 pi-type display pll fast mode lines. (*256) dpl_pd_max 7: 0 default : 0x10 access : r/w abh dpl_pd_max 7:0 pi-type display pll phase detector (dpl_pd) limit. if bit[7]=1, force using bit[6:0]. dpl_pd_max_v cr 7: 0 default : 0xff access : r/w ach dpl_pd_max_vcr 7:0 pi-type display pll phase detector (dpl_pd) limit for vcr ouside vsync area. reg_656_ctrl 7: 0 default : 0x3a access : r/w reg_656_optio n1 7 line middle method 0 selection. reg_656_optio n0 6 line middle method 1 selection. reg_dpl_wait_leng 5:4 dpl wait length. reg_dpl_nco_rst 3 dpl nco reset enable. dpl_fast_re_do 2 pi-type display pll re-do fast mode. dpl_no_stop 1 pi-type display pll never stops. (free run when hsync not found.) adh dpl_coast_t_force 0 pi-type display pll frequency frozen always. (except when fast mode and initialization) dpl_coast_ctrl 7: 0 default : 0xb8 access : r/w vsync_sel 7 vsyn c source selection. - 6 reserved. coast_v_alwa ys 5 always v coast function. aeh dpl_coast_t_lines 4:0 lines where 656 pll coast frequency during v. pi-type display pll frequency frozen lines during vsync. (*2) dpl_ctrl2 7: 0 default : 0x85 access : r/w dpl_lost_line s 7:4 pi-type dislay pll threshold on lines to determine out-of C lock. (*64). afh dpl_lost_wi n 3:0 pi-type display pll hsync window width to detect out-of-lock. (*8) dpl_k1_fr ee 7: 0 default : 0x86 access : r/w dpl_k1_free 7:4 pi-type dipslay pll phase tracking coefficient during hsync not found. b0h bkprh_jump_max 3:0 back-porch-jump maximal lines. (try.) (can move to sw clmp.) b1h bkprh_jump_ctrl 7: 0 default : 0x06 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 114 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description - 7 reserved. bkprh_jump_mv_en 6:5 back-porch-jump used to pause clamping when macrovision found (if set 01). (try.) (can move to sw clmp.) bkprh_jump_thrd 4:0 back-porch-jump threshold. (*32+32). (try.) (can move to sw clmp.) spl_delay_fi r 7: 0 default : 0x19 access : r/w - 7:6 reserved. b2h spl_delay_fir 5:0 coarse hsync pll delay with respect to the actual hsync leading edge if sync_inmux selects cctrap or cctrap_13. spl_delay_ii r 7: 0 default : 0x1e access : r/w - 7 reserved. b3h spl_delay_iir 6:0 coarse hsync pll delay with respect to the actual hsync leading edge if sync_inmux selects iir_8 or iir_16. reg_pb_ctrl 7: 0 default : 0x00 access : r/w reg_pb_en 7 0 : hold adc data probe. 1: enable adc data probe. reg_pb_4fsc 6 0 : probe 8fsc adc data when 8fsc clock. 1: probe 4fsc adc data when 8fsc clock. reg_pb_line 5: 4 1: probe adc data in next line. reg_pb_yc 3 0 : probe y(cbvs) adc data. 1: probe c adc data. reg_pb_10b 2 0 : probe 8 bit data. 1: probe 10 bit data. b4h - 1:0 reserved. probe_out 7: 0 default : 0x00 access : r b5h probe_out 7:0 adc probe data. (rp_lsb) ? {6 b0, probe_out1[1:0]} : probe_out1[9:2]. reg_pb_hpos 7: 0 default : 0x00 access : r/w b6h reg_pb_hpos[7:0] 7: 0 start probe horizontal position. (lower 8 bits) reg_pb_bpos 1 7: 0 default : 0x00 access : r/w - 7:6 reserved. reg_pb_vpos[10:8] 5: 4 start probe vertical position. (upper 3 bits) b7h reg_pb_hpos[10:8] 2: 0 start probe horizontal position. (upper 3 bits) mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 115 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. video decoder register (bank = 02) index name bits description reg_pb_vpos 2 7: 0 default : 0x00 access : r/w b8h reg_pb_vpos[7:0] 7: 0 start probe vertical position. (lower 8 bits) reg_wp_hover thrd 7: 0 default : 0x1f access : r/w b9h reg_wp_hover thrd[7:0] 7:0 overflow threshold of adc value. reg_wp_hundert hrd 7: 0 default : 0x1f access : r/w bah reg_wp_hunder thrd[7:0] 7: 0 underflow threshold of adc value. - 7: 0 default : - access : - bbh ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 116 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank = 03, registers 01h ~ 9fh) comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description - 7: 0 default : 0x00 access : r/w 00h ~ 09h - 7:0 reserved. combcfga 7: 0 default : 0x12 access : r/w - 7 reserved. svdocbp 6 band pass filter for s-video c channel to kill the dc level. diradcin 5 direct use adc input (bypass afec). ddetsrcsel 4 degree detect source select. 0: without acc. 1: after acc. manucomb 3 0 : auto select working mode. 1: manual select working mode. 10h workmd 2:0 working mode. 000: off. 001: notch. 010: 2d comb. 011: 3d comb. 100: 3d comb with history. combcfgb 7: 0 default : 0x00 access : r/w force8bit 7 force 8 bit. goodhs 6 us ing free run hsync in standard input. afec_dem 5 se lect afec demodulation. palcminv 4 palcmpup inverse. - 3 reserved. syncony 2 syn c on y. crma_off 1 turn off the chroma of video decoder output. 0: normal. 1: off. 11h bst_off 0 turn off the color burst of video decoder output. 0: normal. 1: off. combcfgc 7: 0 default : 0x10 access : r/w freesync 7 h /v sync free run. 12h freecntmd 6 free run counter mode. 0: ntsc. 1: pal. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 117 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description snowtype 5: 4 snow type. 00: never snow. 01: snow when vdomd = 7. 10, 11: force snow. rnd_md 3:2 rounding mode. 00: truncate. 01: rounding. 10: dithering. 11: error feedback. - 1:0 reserved. ygain 7: 0 default : 0xc8 access : r/w 13h ygain 7:0 luma gain for u/v demodulation. out=in*gain+16. 0: 0. 128: 1. 255: 1.992. cbgain 7: 0 default : 0x96 access : r/w 14h cbgain 7:0 cb gain for u/v demodulation. crgain 7: 0 default : 0x6a access : r/w 15h crgain 7:0 cr gain for u/v demodulation. dithctrla 7: 0 default : 0x00 access : r/w - 7 reserved. ctstdithen 6 dithering when contrast adjustment. ctstdithpos 5:4 dithering position (offset) of contrast. - 3 reserved. satdithen 2 dithering when saturation adjustment. 16h satdithpos 1:0 dithering position (offset) of saturation. dithctrlb 7: 0 default : 0x00 access : r/w - 7 reserved. ydemdithen 6 dithering when demodulation y-gain. ydemdithpos 5:4 dithering position (offset) of y gain. - 3 reserved. cdemdithen 2 dithering when demodulation c-gain. 17h cdemdithpos 1:0 dithering position (offset) of c gain. 18h horstpos 7: 0 default : 0xc0 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 118 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description horstpos[7:0] 7: 0 horizontal starting position. 0..255 : -128..127. frhtotl 7: 0 default : 0x8d access : r/w 19h frhtotl 7:0 free run hsync total low byte. frhtoth 7: 0 default : 0x03 access : r/w 1ah frhtoth 7:0 free run hsync total high byte. phsdetcfg 7: 0 default : 0x83 access : r/w phsdeten 7 line-lock phase detection enable. phsdetinv 6 output inverse. - 5:3 reserved. 1bh phsdetsft 2: 0 shift bit number. 000: only output integer. 001: output shift right 1 bit. 111: output shift right 7 bit. ctrlswch 7: 0 default : 0xf0 access : r/w hsfrafec 7 h -sync from afec. vsfrafec 6 v -sync from afec. blkfrafec 5 black level from afec. degfrafec 4 demodulation degree from afec. - 3:2 reserved. stdsel 1: 0 ntsc/pal decision. 01: force ntsc. 10: force pal. other: auto detect. comb2dcfga 7: 0 default : 0x00 access : r/w 20h - 7:0 reserved. comb2dcf gb 7: 0 default : 0xd4 access : r/w crmatrp_en 7 c-trap of c enable. nchmd_y[2:0] 6: 4 notch mode of y. chrmflt_en 3 chroma median filter enable. 0: off 1: enable 21h nchmd_c[2:0] 2: 0 notch mode of c. 22h comb2dcf gc 7: 0 default : 0x83 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 119 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description lnendpos 7:4 line end offset. 0~15: -8~7. sharp2dmd 3: 2 sharpness mode of 2d comb. 00: off. 01: mode 1. 10: mode 2. 11: mode 3. cdemchk 1 chroma vertical check (dem). force5ln 0 force use 5 line even in 1d. hdygain 7: 0 default : 0x40 access : r/w 23h hdygain 7: 0 gain of chroma trap for hanging dots. hdcgain 7: 0 default : 0x20 access : r/w 24h hdcgain 7: 0 gain of chroma trap for hanging dots. etpref 7: 0 default : 0x18 access : r/w 25h etpref 7: 0 gain of chroma trap for hanging dots. etpthh 7: 0 default : 0x00 access : r/w 26h etpthh 7: 0 horizontal entropy threshold for chroma trap in 2d comb. etpthv 7: 0 default : 0x00 access : r/w 27h etpthv 7: 0 vertical entropy threshold for chroma trap in 2d comb. thdem 7: 0 default : 0x10 access : r/w 28h thdem 7:0 thresholds for 2d comb filter; check separated chroma complement with up/down line or not. - 7: 0 default : - access : - 29h ~ 2eh - 7:0 reserved. ifcoef 7: 0 default : 0x00 access : r/w 2fh ifcoef 7:0 if compensation coefficient. 2-bit integer, 6-bit fraction. crma=c_cn C (coef*(c_left+c_right)). - 7: 0 default : - access : - 30h ~ 3fh - 7:0 reserved. hvdetcfg 7: 0 default : 0x80 access : r/w senssynclvl 7: 5 sensitivity of sync level detect. 40h - 4:3 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 120 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description blnkdetmd 2 blank level detect mode. 0: either 240 or 252. 1: 230~262 is possible. vdetmd 1: 0 vertical timing detect mode. 00, 01: auto detect. 10: force 525 line system. 11: force 625 line system. senssigdet 7: 0 default : 0x08 access : r/w 41h senssigdet 7: 0 sensitivity of signal detect. synclvltlrn 7: 0 default : 0xff access : r/w 42h synclvltlrn 7: 0 sync level tolerance. vcrcoastlen 7: 0 default : 0x60 access : r/w 43h vcrcoastlen 7: 0 vcr coast length. reghbidly 7: 0 default : 0x80 access : r/w 44h reghbidly 7: 0 horizontal blanking region delay. 0 255 : delay -128 .. 127 pixels. - 7: 0 default : - access : - 45h ~ 47h - 7:0 reserved. degdetcfg 7: 0 default : 0x00 access : r/w ycpipe 7: 6 y/c pipe delay. degpipe 5:4 degree pipe delay. deg1lnmd 3 us ing just one line s burst determine the degree. 48h degsens 2: 0 sensitivity of degree detect. 000: directly use afec degree. 001: tolerate 16384 errors. 010: tolerate 8192 errors. 011: tolerate 4096 errors. 100: tolerate 2048 errors. 101: tolerate 1024 errors. 110: tolerate 512 errors. 111: tolerate 256 errors. thburst 7: 0 default : 0x1e access : r/w 49h thburst 7:0 degree detection tolerance registers. tlrnswch err 7: 0 default : 0xc8 access : r/w 4ah tlrnswcherr 7:0 degree detection tolerance registers. 4bh hsleadrgn 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 121 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description hsleadrgn 7: 0 hsync leading edge range, for even/odd detect. - 7: 0 default : - access : - 4ch ~ 4fh - 7:0 reserved. timdetcfga 7: 0 default : 0x07 access : r/w - 7:4 reserved. autostopsync 3 automatic stop h/v sync when no input. 50h lnfreemd 2:0 line buffer free run mode. 000: off (always synchronize). 001: 909 return. 010: 910 return. 011: 917 return. 100: 1127 return. 101: 1135 return. 110: decided by register. 111: automatic. timdetcfgb 7: 0 default : 0x00 access : r/w stbcntmd 7: 6 stable counter mode. 00: div 16. 01: div 32. 10: div 64. 11: div 128. 51h hsstbdec 5: 0 hsync stable counter decrease speed. hretposl 7: 0 default : 0x8e access : r/w 52h hretposl 7: 0 horizontal return position in line buffer free run mode. hretposh 7: 0 default : 0x03 access : r/w 53h hretposh 7: 0 horizontal return position in line buffer free run mode. tilttlrn 7: 0 default : 0x02 access : r/w 54h tilttlrn 7:0 line position tilt tolerance. jittlrn 3d 7: 0 default : 0x08 access : r/w 55h jittlrn3d 7: 0 3d timing detection tolerance. lckstep 7: 0 default : 0x80 access : r/w 56h lckstep 7: 0 3d lock counter go back distance when sync unstable. lck3dthu 7: 0 default : 0x33 access : r/w 57h lck3dthu 7: 0 3d timing detection threshold. lck3dthl 7: 0 default : 0x11 access : r/w 58h lck3dthl 7: 0 3d timing detection threshold. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 122 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description jittlrn1 7: 0 default : 0x08 access : r/w 59h jittlrn1 7:0 tolerance of h-sync jitter. jittlrn2 7: 0 default : 0x20 access : r/w 5ah jittlrn2 7:0 tolerance of h-sync jitter. hslckthu 7: 0 default : 0x10 access : r/w 5bh hslckthu 7: 0 upper bound threshold of hysteresis h-sync lock counter. hslckthl 7: 0 default : 0x08 access : r/w 5ch hslckthl 7:0 lower bound threshold of hysteresis h-sync lock counter. hschgtlrn 7: 0 default : 0xff access : r/w 5dh hschgtlrn 7:0 tolerance of hsync counter change times. even hsync locked, but if timing drifted too many times, systme still should turn off 2d/3d. 00h: immediately stop 2d/3d when hschg happen. ffh: never stop 2d/3d if hslock. syncdly 7: 0 default : 0x14 access : r/w 5eh syncdly 7: 0 h sync (from decoder to scaler) pipe delay. - 7: 0 default : - access : - 5fh - 7:0 reserved. imgctrl 7: 0 default : 0xf0 access : r/w colkillmd 7:6 color kill mode. 00: off. 01: auto. 10, 11: decided by mcu. cgmode 5:4 auto chroma gain mode. 00: off. 01: auto. 10, 11: manual. ac_md 3 auto contrast mode. 0: double at most. 1: 4 times at most. auto_csts 2 auto contrast adjustment. - 1 reserved. 60h auto_sat 0 auto saturation adjustment. rspntime 7: 0 default : 0x10 access : r/w 61h rspntime 7:0 response time of contrast/brightness adjust. 0 255 => 1 256 field. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 123 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description regbsthght 7: 0 default : 0x00 access : r/w 62h regbsthght 7:0 burst height for auto chroma gain. 0: auto, 112 for ntsc and 117 for pal. other: use regbsthght/detbsthght as c gain. regctst 7: 0 default : 0x80 access : r/w 63h regctst 7:0 contrast adjustment coefficient. 0 255 => 0 (255/128). regbrht 7: 0 default : 0x80 access : r/w 64h regbrht 7:0 brightness adjustment coefficient. 0 255 => -128 127 in 8-bit precision. regsat 7: 0 default : 0x80 access : r/w 65h regsat 7: 0 saturation adjustment coefficient. 0 255 => (0 255)/128. ckthu 7: 0 default : 0x80 access : r/w 66h ckthu 7: 0 upper bound threshold of color kill. ckthl 7: 0 default : 0x30 access : r/w 67h ckthl 7:0 lower bound threshold of color kill. crmagainl 7: 0 default : 0x80 access : r/w 68h crmagainl 7:0 chroma gain value for manu chroma gain. crmagainh 7: 0 default : 0x00 access : r/w 69h crmagainh 7:0 chroma gain value for manu chroma gain. maxluma 7: 0 default : 0xb0 access : r/w 6ah macluma 7:0 max luminance for auto contrast adjust. maxsat 7: 0 default : 0xc0 access : r/w 6bh maxsat 7:0 max saturation for auto saturation adjust. maxcrma 7: 0 default : 0xc0 access : r/w 6ch maxcrma 7:0 max chrominance for auto saturation adjust. snowdelay 7: 0 default : 0x80 access : r/w 6dh snowdelay 7:0 latency of snow output after signal missing. - 7: 0 default : - access : - 6eh - 7:0 reserved. 6fh cbcrlpcfg 7: 0 default : 0x04 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 124 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description ctiiirmd 7:6 iir coeficient for cti. 00: 1/4. 01: 1/8. 10: 1/16. 11: 1/32. ctimode 5:4 cti mode. 00: off. 01: weak. 10: normal. 11: strong. ypipdly 3:2 luma pipe delay. 00: -1 cycle. 01: 0 cycle. 10: 1 cycle. 11: 2 cycle. cbcrlpmd 1:0 cb/cr low pass mode. 0: off. 01: cut off at 2.0mhz. 10: cut off at 1.5mhz. 11: cut off at 1.0mhz combstatusa 7: 0 default : - access : write one clear hslock 7 hsync lock happen. lock3d 6 g ood timing (lock3d) happen. - 5:4 reserved. hslockz 3 hs ync unlock happen. loc3dz 2 g ood timing (lock3d) disappear. hschg 1 h -sync counter change. 70h - 0 reserved. combstatus b 7: 0 default : - access : write one clear - 7:6 reserved. cchnlact 5 c-channel active (maybe s-video input). cchnlact 4 c-channel quiet (maybe cvbs input0. - 3 reserved. fldcntchg 2 field counter change. palswcherr 1 pal switch error. 71h degerr 0 degree error (degree detect). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 125 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description combstatus c 7: 0 default : - access : ro ln525 7 525 line system. ln625 6 625 line system. f358 5 3 .58 mhz system. f443 4 4 .43 mhz system. noinput 3 n o input. 72h vdomd 2: 0 video mode. 000: ntsc(m). 001: ntsc(443). 010: pal (m). 011: pal(b,d,g,h,i,n). 100: pal(nc). 101: pal(60). 110: input without burst. 111: unknown. detblanklvl 7: 0 default : - access : ro 73h detblanklvl 7:0 detected blanking level. curblanklvl 7: 0 default : - access : ro 74h curblanklvl 7:0 detected blanking level. detsynclvl 7: 0 default :- access : ro 75h detsynclvl 7:0 detected sync level. detsynchght 7: 0 default : - access : ro 76h detsynchght 7:0 detected sync height. detbursthght 7: 0 default : - access : ro 77h detbursthght 7:0 detected burst level. dethortotall 7: 0 default : - access : ro 78h dethortotall 7: 0 dethortotalh 7: 0 default : - access : r 79h dethortotal h 7: 0 - 7: 0 default : - access : - 7ah ~ 7ch - 7:0 reserved. combctrl 7: 0 default : 0x00 access : r/w 7dh combctrl 7: 0 some control signals for fpga. - 7: 0 default : - access : - 7eh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 126 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. comb-filter register (bank=03, registers 01h ~ 9fh) index name bits description fpgactrl 7: 0 default : 0xe0 access : r/w 7fh fpgactrl 7: 0 some control signals for fpga. - 7: 0 default : - access : - 80h ~ 9fh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 127 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. secam register (bank 03, registers a0h ~ ffh) secam register (bank=03, registers a0h ~ ffh) index name bits description - 7: 0 default : - access : - a0h - 7:0 reserved. scm_idset1 7: 0 default : 0x02 access : r/w rst_flt 7 filter reset. set to 1 to reset the vaules of filter taps. mixc_en 6 chroma mixing enable. 0: disable. 1: enable. wfunc_iso 5:4 chroma weighting function isolation. sven 3 s -video input enable. set to 1 if the input is from s-video interface. id_mode 2 identification mode selection. set to 1 only if using frame id for secam detection. bs_type 1 band-stop filter type. 0: notch dr frequency. 1: notch db frequency. a1h scmid_en 0 s ecam identification forced enable. 0: disbale. 1: enable. sample_start 7: 0 default : 0x90 access : r/w a2h sample_st[7:0] 7: 0 start of sample point (lower 8 bits). sample_length 7: 0 default : 0x10 access : r/w a3h sample_len 7:0 length of sample numbers. line_start_a 7: 0 default : 0x07 access : r/w a4h line_sta 7: 0 start of line number of odd filed. line_start _b 7: 0 default : 0x40 access : r/w a5h line_stb[7:0] 7: 0 start of line number of even filed (lower 8 bits). scm_idset2 7: 0 default : 0x01 access : r/w - 7 reserved. sample_st[10:8] 6: 4 start of sample point (upper 3 bits). cmbgclk_opt 3 comb clock gating option. 0: diable. 1: enable clkcomb gating. a6h - 2 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 128 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. secam register (bank=03, registers a0h ~ ffh) index name bits description line_stb[9:8] 1: 0 start of line number of even filed (upper 2 bits). line_length 7: 0 default : 0x02 access : f/w a7h line_len 7:0 length of observation line. act_multipl e 7: 0 default : 0x96 access : r/w a8h act_multiple 7:0 integer multiple of line_len, combined to form length of the active video line. mag_thrsd_l 7: 0 default : 0x00 access : r/w a9h mag_thrsd[7:0] 7:0 magnitude threshold (lower 8 bits). mag_thrsd_m 7: 0 default : 0x06 access : aah mag_thrsd[15:8] 7:0 magnitude threshold (middle 8 bits). mag_thrsd_h 7: 0 default : 0x40 access : r/w - 7 reserved. line_pixnum[10:8] 6:4 pixel number of line buffer (upper 3 bits). abh mag_thrsd[19:16] 3:0 magnitude threshold (upper 4 bits). line_pixnum ber 7: 0 default : 0x48 access : r/w ach line_pixnum[7:0] 7:0 pixel number of line buffer (lower 8 bits). (if the number is 1097, program 11 h448) id_thrsd 7: 0 default : 0x06 access : r/w adh id_thrsd 7:0 threshold for secam identification. scm_thrsd 7: 0 default : 0x66 access : r/w nonscm_thrsd 7: 4 non-secam decision threshold. aeh scm_thrsd 3: 0 secam decision threshold. - 7: 0 default : - access : - afh ~ cfh - 7:0 reserved. scm_idstatus 7: 0 default : - access : r scmid_done 7 s ecam identification done indication. scmid_yes 6 s ecam signal found bit. dr_line 5 dr line indication. db_line 4 db line indication. - 3 reserved. d0h scmid_sts 2: 0 secam id status. 000: idle 001, 010, 011: id progress 110: secam 111: no secam signal discovery mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 129 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. secam register (bank=03, registers a0h ~ ffh) index name bits description mag_int_l 7: 0 default : - access : r d1h mag_int[7:0] 7:0 magnitude accumulated values for observation (lower 8 bits). mag_int_m 7: 0 default : - access : r d2h mag_int[15:8] 7:0 magnitude accumulated values for observation (middle 8 bits). mag_int_h 7: 0 default : - access : r mag_intb[19:16] 7:4 magnitude accumulated values for observation (upper 4 bits). d3h mag_int[19:16] 3:0 magnitude accumulated values for observation (upper 4 bits). mag_int_b_l 7: 0 default : - access : r d4h mag_intb[7:0] 7:0 magnitude accumulated values for observation (lower 8 bits). mag_int_b_m 7: 0 default : - access : r d5h mag_intb[15:8] 7:0 magnitude accumulated values for observation (meddle 8 bits). scm_fsc 7: 0 default : - access : r - 7:2 reserved. d6h scm_fsc 1:0 fsc status from afec_top. 00: ntsc 3.58mhz 01: pal 4.43mhz 10: secam 4.285156mhz - 7: 0 default : - access : - d7h ~ f1h - 7:0 reserved. wr_lk1 7: 0 default : 0x00 access : r/w wr_lk1 7 register lock (work with wr_lk0). register access is disabled when wr_lk0 and wr_lk1 are high. register access is enabled when wr_lk0 and wr_lk1 are low. f2h - 6:0 reserved. pwmclk 7: 0 default : 0x00 access : r/w db_en 7 double buffer enable. 0: disable. 1: enable. p4ren 6 pwm4 reset every frame enable. 0: disable. 1: enable. p3ren 5 pwm3 reset every frame enable. 0: disable. 1: enable. f3h p4pol 4 pwm 4 polarity when enhance pwm4 enable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 130 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. secam register (bank=03, registers a0h ~ ffh) index name bits description ep4en 3 enhance pwm4 enable. 0: disable. 1: enable. p3pol 2 pwm3 polarity when enhance pwm3 enable. ep3en 1 enhance pwm3 enable. 0: disable. 1: enable. pclk 0 pwm3/4 base clock select. 0: 14.318mhz. 1: 14.318mhz / 4. pwm3c 7: 0 default : 0x00 access : r/w pwm_14bit_en 7 14 bit pwm enable. 0: disable, then pwm3c[6:0] = pwm3_ctun[6:0]. 1: enable, then pwm3c[3:0] = pwm_div. pwm3_ctun[6:0] 6:0 pwm3 coarse adjustment, when pwm_14bit_en = 0. - 6:4 reserved. f4h pwm_div 3:0 clock divider, when pwm_14bit_en = 1. pwm4c 7: 0 default : 0x00 access : r/w pwm4_pol 7 pwm4 polarity. f5h pwm4_ctun[6:0] 6:0 pwm4 coarse adjustment. pwm3epl 7: 0 default : 0x00 access : r/w epwm0p[7:0] 7:0 enhance pwm3 period, when pwm_14bit_en = 0. f6h pwm_fine_tune 7:0 fine tune pwm pulse, when pwm_14bit_en = 1. pwm3eph 7: 0 default : 0x00 access : r/w epwm0p[15:8] 7:0 enhance pwm3 period, when pwm_14bit_en = 0. f7h pwm_mask_bit 5:0 mask pwn period bits, when pwm_14bit_en = 1. pwm4epl 7: 0 default : 0x00 access : r/w f8h epwm4p[7:0] 7:0 enhance pwm4 period. pwm4eph 7: 0 default : 0x00 access : r/w f9h epwm4p[15:8] 7:0 enhance pwm4 period. pwm3c_t 7: 0 default : 0x00 access : r/w - 7:5 reserved. fah pwm3_pol 4 pwm3 polarity. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 131 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. secam register (bank=03, registers a0h ~ ffh) index name bits description - 3:0 reserved. - 7: 0 default : - access : - fbh ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 132 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. embedded mcu register (address mapping from c000h to c0ffh) embedded mcu register bank C general control register index name bits description - 7: 0 default : - access : - 00h ~ 07h - 7:0 reserved. wdt_key_l 7: 0 default : 0xaa access : r/w 08h wdt_key[7:0] 7:0 watchdog timer disable key low byte watchdog timer will be enabled if (wdt_key_l != 8 haa) or (wdt_key_h != 8 h55) wdt_key_h 7: 0 default : 0x55 access : r/w 09h wdt_key[15:8] 7:0 refer to c008h. - 7: 0 default : - access : - 0ah - 7:0 reserved. ddc2bi_int_en 6: 0 default: 0x00 access : r/w start_en 6 ddc2bi start interrupt enable. stop_en 5 ddc2bi stop interrupt enable. datr_en 4 ddc2bi data reda interrupt enable. datw_en 3 ddc2bi data write interrupt enable. datrw_en 2 ddc2bi data read/write interrupt enable. wadr 1 ddc2bi word address interrupt. 10h id 0 ddc2bi id interrupt. ddc2bi_flag 6: 0 default : 0x00 access : r/c 11h ddc2bi_flag ddc 2bi interrupt flag and clear ddc2bi_w_buf 7: 0 default : - access : ro 12h ddc 2bi write, mcu read buffer ddc2bi_r_buf 7: 0 default : 0x00 access : r/w 13h ddc2bi_r_buf[7:0] 7:0 ddc2bi read, mcu write buffer - 7: 0 default : - access : - 14h ~ 17h - 7:0 reserved. ddc2bi_ctrl 1: 0 default : 0x00 access : r/w - 7:2 reserved. en_no_ack 1 ddc2bi does not send ack if data buffer has not been read. 0: disable. 1: enable. 18h - 0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 133 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. embedded mcu register bank C general control register index name bits description ddc2bi_id 7: 0 default : 0x00 access : r/w ddc2bi_en 7 ddc2bi enable. 19h ddc2bi_id[6:0] 6:0 ddcbi id. - 7: 0 default : - access : - 1ah ~ 1fh - 7:0 reserved. key_adc1 5: 0 default : - access : ro 20h key_adc1[5:0] key pad adc channel 1 value. key_adc2 5: 0 default : - access : ro 21h key_adc2[5:0] key pad adc channel 2 value. key_adc3 5: 0 default : - access : ro 22h key_adc3[5:0] key pad adc channel 3 value. - 7: 0 default : - access : - 23h ~ 2fh - 7:0 reserved. p0_ctrl 7: 0 default : 0x00 access : r/w 30h p0_ctrl[7:0] 7:0 mcu port 0 output enable control. p0_oe 7: 0 default : 0x00 access : r/w 31h p0_oe[7:0] 7:0 mcu port 0 output enable. p0_in 7: 0 default : 0x00 access : r/w 32h p0_in[7:0] 7:0 mcu port 0 output enable from output data. p1_ctrl 7: 0 default : 0x00 access : r/w 33h p1_ctrl[7:0] 7:0 mcu port 1 output enable control. p1_oe 7: 0 default : 0x00 access : r/w 34h p1_oe[7:0] 7:0 mcu port 1 output enable. p1_in 7: 0 default : 0x00 access : r/w 35h p1_in[7:0] 7:0 mcu port 1 output enable from output data. p2_ctrl 7: 0 default : 0x00 access : r/w 36h p2_ctrl[7:0] 7:0 mcu port 2 output enable control. p2_oe 7: 0 default : 0x00 access : r/w 37h p2_oe[7:0] 7:0 mcu port 2 output enable. p2_in 7: 0 default : 0x00 access : r/w 38h p2_in[7:0] 7:0 mcu port 2 output enable from output data. p3_ctrl 7: 0 default : 0x00 access : r/w 39h p3_ctrl[7:0] 7:0 mcu port 3 output enable control. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 134 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. embedded mcu register bank C general control register index name bits description p3_oe 7: 0 default : 0x00 access : r/w 3ah p3_oe[7:0] 7:0 mcu port 3 output enable. p3_in 7: 0 default : 0x00 access : r/w 3bh p3_in[7:0] 7:0 mcu port 3 output enable from output data. p4_ctrl 7: 0 default : 0x00 access : r/w 3ch p4_ctrl[7:0] 7:0 mcu port 4 output enable control. p4_oe 7: 0 default : 0x00 access : r/w 3dh p4_oe[7:0] 7:0 mcu port 4 output enable. p4_in 7: 0 default : 0x00 access : r/w 3eh p4_in[7:0] 7:0 mcu port 4 output enable from output data. sspi_sts_op 7: 0 default : 0x05 access : r/w 3fh sppi_sts_op[7:0] 7: 0 soft-trigger spi check status op code. sspi_wd0 7: 0 default : 0x00 access : r/w 40h sspi_wd0 7: 0 soft-trigger spi write byte 0. sspi_wd1 7: 0 default : 0x00 access : r/w 41h sspi_wd1 7: 0 soft-trigger spi write byte 1. sspi_wd2 7: 0 default : 0x00 access : r/w 42h sspi_wd2 7: 0 soft-trigger spi write byte 2. sspi_wd3 7: 0 default : 0x00 access : r/w 43h sspi_wd3 7: 0 soft-trigger spi write byte 3. sspi_wd4 7: 0 default : 0x00 access : r/w 44h sspi_wd4 7: 0 soft-trigger spi write byte 4. sspi_wd5 7: 0 default : 0x00 access : r/w 45h sspi_wd5 7: 0 soft-trigger spi write byte 5. sspi_wd6 7: 0 default : 0x00 access : r/w 46h sspi_wd06 7: 0 soft-trigger spi write byte 6. sspi_wd7 7: 0 default : 0x00 access : r/w 47h sspi_wd7 7: 0 soft-trigger spi write byte 7. sspi_trig 7: 0 default : 0x00 access : r/w sspi_start 7 trigger soft-spi 0: nop. 1: start soft -spi. sspi_chk_bzy 6 auto check busy after soft-spi. 48h sspi_chk_bit 5:3 check busy bit position mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 135 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. embedded mcu register bank C general control register index name bits description sspi_length 2: 0 sspi command length. sspi_rd1 7: 0 default : - access : ro 49h sspi_rd1[7:0] 7: 0 sspi read byte 1. sspi_rd2 7: 0 default : - access : ro 4ah sspi_rd2[7:0] 7: 0 sspi read byte21. sspi_rd3 7: 0 default : - access : ro 4bh sspi_rd3[7:0] 7: 0 sspi read byte 3. sspi_rd4 7: 0 default : - access : ro 4ch sspi_rd4[7:0] 7: 0 sspi read byte 4. sspi_rd5 7: 0 default : - access : ro 4dh sspi_rd5[7:0] 7: 0 sspi read byte 5. sspi_rd6 7: 0 default : - access : ro 4eh sspi_rd6[7:0] 7: 0 sspi read byte 6. sspi_rd7 7: 0 default : - access : ro 4fh sspi_rd7[7:0] 7: 0 sspi read byte 7. isp_pa0 7: 0 default : 0x00 access : r/w 50h isp_pa[7:0] 7:0 parallel flash isp address[7:0]. isp_pa1 7: 0 default : 0x00 access : r/w 51h isp_pa[15:8] 7:0 parallel flash isp address[15:8]. isp_pa2 7: 0 default : 0x00 access : r/w 52h isp_pa[17:16] 7:0 parallel flash isp address[17:16]. isp_pd_w 7: 0 default : 0x00 access : r/w 53h isp_pd_w[7:0] 7:0 parallel flash isp write data. isp_pctr 4: 0 default : 0x0a access : r/w isp_pmd_en 4 parallel flash isp mode enable. isp_pwez 3 parallel flash wez at isp mode. isp_poez 2 parallel flash oez at isp mode. isp_pdbue 1 parallel flash data bus output enable at isp mode. 54h isp_pcez 0 parallel flash cez at isp mode. isp_pd_r 7: 0 default :- access : ro 55h isp_pd_r[7:0] 7:0 parallel flash isp mode read data. - 7: 0 default : - access : - 56h ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 136 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. lvds register (bank = 04, registers 01h ~ 6ah) lvds register (bank = 04, registers 01h ~ 6ah) index name bits description - 7: 0 default : - access : - 01h ~ 0fh - 7:0 reserved. gpoa_ctrl 7: 0 default : 0x00 access : r/w gcs 7: 5 select gpo source. gts 4:3 control skip line number. - 2 reserved. gtc 1 se lect gpo_i source. 10h gop 0 se lect gpo_i source. gavst_l 7: 0 default : 0x00 access : r/w 11h gpoa_vst[7:0] 7: 0 gpoa vstar point (lower 8 bits). gavst_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 12h gpoa_vst[10:8] 2: 0 gpoa vstar point (upper 3 bits). gavend_l 7: 0 default : 0x00 access : r/w 13h gpoa_vend[7:0] 7: 0 gpoa vend (lower 8 bits). gavend_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 14h gpoa_vend[10:8] 2: 0 gpoa vend (upper 3 bits). gahst_l 7: 0 default : 0x00 access : r/w 15h gpoa_hst[7:0] 7: 0 gpoa hstar (lower 8 bits). gahst_h 7: 0 default : 0x00 access : r/w - 7:3 reserved. 16h gpoa_hst[10:8] 2: 0 gpoa hstar (upper 3 bits). gahend_l 7: 0 default : 0x00 access : r/w 17h gpoa_hend[7:0] 7: 0 gpoa hend (lower 8 bits). ga_hend_h 7: 0 default : 0x00 access : r/w - 7:4 reserved. 18h gpoa_hend[10:8] 3: 0 gpoa hend (upper 3 bits). lvds_ctrl 7: 0 default : 0x00 access : r/w - 7:6 reserved. gpoa_gated_e n 5 clock gated using gpoa singal. 19h add_1 4 h ard clock gated pulse width add one. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 137 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. lvds register (bank = 04, registers 01h ~ 6ah) index name bits description t_lvdssel 3 lvds test enable. ch_swap 2 channel switch. ch_polarity 1 channel value invert. lvds_ti 0 lvds ti type. lvds_test 7: 0 default : 0x00 access : r/w 1ah tester_pix 7:0 lvds test pixel. mod_tdr0 7: 0 default : 0x00 access : r/w 1bh drvn_ttl[7:0] 7:0 output driving of n_channel when mod is ttl output (lower 8 bits). mod_tdr1 7: 0 default : 0x00 access : r/w drvp_ttl[5:0] 7:2 output driving of p_channel when mod is ttl output (lower 6 bits). 1ch drvn_ttl[9:8] 1:0 output driving of n_channel when mod is ttl output (upper 2 bits). mod_tdr2 7: 0 default : 0x00 access : r/w - 7:4 reserved. 1dh drvp_ttl[9:6] 3:0 output driving of p_channel when mod is ttl output (upper 4 bits). mod_ctrl 7: 0 default : 0x00 access : r/w - 7:3 reserved. mod_pwdn 2 mod power down. mod_clk_en 1 mod clock enable. 1eh half_swing_e n 0 lvds_output swing reduce half. - 7: 0 default : - access : - 1fh - 7:0 reserved. mod_sel0 7: 0 default : 0x00 access : r/w - 7:5 reserved. 20h selgpo 4: 0 select gpo. mod_sel1 7: 0 default : 0xff access : r/w - 7:5 reserved. 21h selttl 4: 0 select ttl. lvds_t0 7: 0 default : 0x06 access : r/w 22h test_lvds[7:0] 7:0 lvds test bits (lower 8 bits). 23 h lvds_t1 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 138 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. lvds register (bank = 04, registers 01h ~ 6ah) index name bits description test_lvds[15:8] 7:0 lvds test bits (upper 8 bits). lvds_tri0 7: 0 default : 0xff access : r/w 24h lvds_tri[7:0] 7:0 lvds tri_state (lower 8 bits). lvds_tri1 7: 0 default : 0xff access : r/w - 7:2 reserved. 25h lvds_tri[15:8] 1:0 lvds tri_state (upper 8 bits). reg044c 7: 0 default : 0x00 access : r/w 26h (044ch) 26h_data[7:0] 7:0 [7:0]:low byte of bvcom_dc[8:0], pad_vcomdc voltage adjust, dc : 1.165v~2.327v. reg044e 7: 0 default : 0x00 access : r/w 27h (044eh) 27h_data[7:0] 7:0 [7:4]: tst_ivcom, vcom opamps driving strength select. [3]: reserve. [2]: high bit of bvcom_dc[8:0], pad_vcomdc voltage adjust, dc : 1.165v~2.327v. [1]: tst_vcombgo, vbg output to pad_vcomout. [0]: pwdn_vcom, vcom power down control, 1: power down. reg0450 7: 0 default : 0x00 access : r/w 28h (0450h) 28h_data[7:0] 7:0 [7:0]: bvcom_out, pad_vcomout voltage adjust, vlow/vhigh : 0.45v/2.55v~1.05v/1.95v. reg0452 7: 0 default : 0x00 access : r/w 29h (0452h) 29h_data[7:0] 7:0 [7]: gcr_cal_en_sw, enable software calibration function for lvds output. [6]: gcr_cal_src_sel, select calibration source, 0: ch2, 1: floating. [5:4]: gcr_cal_level_sel, select calibration target voltage. (may change before tape-out). 00: 250mv, 01:300mv, 10: 350mv, 11: 200mv. [3]: gcr_sel_vdd25: mod supply selection, 0: 3.3v, 1: 2.5v. [2:1]: gcr_selvcm: common-mode selection of ch[?:0]. 2.5v 00 = 1.19789 v 01 = 698.769 mv 10 = 1.19789 v 11 = 898.418 mv. 3.3v 00 = 1.58165 v 01 = 922.627 mv 10 = 1.58165 v 11 = 1.18623 v. [0]: gcr_cken, tx clock enable,(lvds) this pin is used for ch0~ch4. reg0454 7: 0 default : 0x00 access : r/w 2ah (0454h) 2ah_data[7:0] 7:0 [7:6]: gcr_outconf_ch3_bit, output mode configuration for channel 3. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 139 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. lvds register (bank = 04, registers 01h ~ 6ah) index name bits description [5:4]: gcr_outconf_ch2_bit, output mode configuration for channel 2. [3:2]: gcr_outconf_ch1_bit, output mode configuration for channel 1. [1:0]: gcr_outconf_ch0_bit, output mode configuration for channel 0. 2'b00: ttl mode/standby mode. 2'b01: lvds/epi/rsds/mini-lvds data output mode. 2'b10: rsds/minilvds clock output mode. 2'b11: test clock output mode. reg0456 7: 0 default : 0x00 access : r/w 2bh (0456h) 2bh_data[7:0] 7:0 [7:6]: skew_reg_g, ttl g data channel output skew control. [5:4]: skew_reg_b, ttl b data channel output skew control. [3]: reserve. [2]: dac test dc level source select, 1:{g7,g4,g3,g2,r6,r2,r1,r0}, 0: htotal[7:0]. [1:0]: gcr_outconf_ch4_bit, output mode configuration for channel 4. 2'b00: ttl mode/standby mode. 2'b01: lvds/epi/rsds/mini-lvds data output mode. 2'b10: rsds/minilvds clock output mode. 2'b11: test clock output mode. reg0458 7: 0 default : 0x00 access : r/w 2ch (0458h) 2ch_data[7:0] 7:0 [7:5]: gcr_outswing_clk_bit[2:0], swing control low bit for ch1,3 when not enable calibration. [4:0]: gcr_outswing_data_bit, swing control for ch0,2,4 when not enable calibration. reg045a 7: 0 default : 0x00 access : r/w 2dh (045ah) 2dh_data[7:0] 7:0 [7:3]: gcr_ds_pol_ch. [2]: gcr_cal_en_hw, enable hardware calibration function for lvds output. [1:0]: gcr_outswing_clk_bit[4:3], swing control high bit for ch1,3 when not enable calibration. reg045c 7: 0 default : 0x00 access : r/w 2eh (045ch) 2eh_data[7:0] 7:0 [7:6]: gcr_peadj_ch3_bit[1:0], differential output pre-emphasis level adjust, low bit of ch3. [5:4]: gcr_peadj_ch2_bit[1:0], differential output pre-emphasis level adjust, low bit of ch2. [3:2]: gcr_peadj_ch1_bit[1:0], differential output pre-emphasis mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 140 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. lvds register (bank = 04, registers 01h ~ 6ah) index name bits description level adjust, low bit of ch1. [1:0]: gcr_peadj_ch0_bit[1:0], differential output data/clock pre-emphasis level adjust, low bit of ch0. (1x means 0.25ma). 0: 0x, 1: 1x, 2: 2x, 3: 3x &. reg045e 7: 0 default : 0x00 access : r/w 2fh (045eh) 2fh_data[7:0] 7:0 [7:3]: gcr_pe_en_ch, differential output pre-emphasis enable for channel [4:0]. [2]: gcr_peadj_max_bit, differential output pre-emphasis level adjust, hight bit of ch0-4. [1:0]: gcr_peadj_ch4_bit[1:0], differential output pre-emphasis level adjust, low bit of ch4. reg0460 7: 0 default : 0x00 access : ro 30h (0460h) 30h_read[7:0] 7:0 [7]: reserve. [6]: dda_out, calibration output. [5]: reg_hw_mod_cal_ready, hardware calibration function finish. [4:0]: reg_gcr_ibcal_hw[4:0], hardware calibration function result. reg0462 7: 0 default : 0x00 access : r/w 31h (0462h) 31h_data[7:0] 7:0 [7]: reg_tpat_en, op2 test pattern enable. [6]: reg_patyuv, yuv type test pattern enable. [5]: reg_pathd,. [4]: reg_patint,. [3:0]: reg_patsel. reg0464 7: 0 default : 0x00 access : r/w 32h (0464h) 32h_data[7:0] 7:0 [7:4]: reg_vpatbsize, vertical size select for test pattern. [7]: enable down count for fix vertical bp. [3:0]: reg_hpatbsize, horizontal size select for test pattern. reg0466 7: 0 default : 0x00 access : r/w 33h (0466h) 33h_data[7:0] 7:0 [7]: reserve. [6:0]: reg_vsync_dcnt, down count line number for fix vertical bp. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 141 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description protect_bit 7: 0 default : 0x00 access : r/w 6bh protect_bit 7: 0 have to set as 1 in that could view all pwm register setting. stus_rprt 7: 0 default : - access : ro - 7:3 reserved. stus_rprt[2] 2 1 : faultz is high. stus_rprt[1] 1 1 : fb2 mode is on. 6ch stus_rprt[0] 0 1 : vin is ok. pwm_swch 7: 0 default : 0x00 access : r/w - 7:2 reserved. 6dh pwm_swch[1:0] 1:0 control pwm on/off; must set to 00 or 11 . 00: pwm off. 11: pwm on. others: off (not recommended). op_md 7: 0 default : 0x00 access : r/w - 7 reserved. pwm_swrst 6 s oftware-reset bit to reset pwm. 0: no action. 1: software reset and remain in initial state using a single pulse. vsync_plrty_sel 5 vsyn c polarity setting. 0: same polarity to vsync. 1: opposite polarity. vsync_sel 4 use tcon s vsync for vsync-mode. 0: use normal vsync. 1: use tcon s vsync. pwm_en 3 pwm function on/off. 0: use external controller. 1: user internal controller. faultz_h_md_e n 2 faultz high mode on/off. 0: off. 1: on. 6eh vsync_md_en 1 vsyn c mode on/off. 0: off. 1: on. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 142 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description brst_md_en 0 burst mode on/off. 0: off. 1: on. vin_stab_cnt 7: 0 default : 0x0a access : r/w 6fh vin_stab_cnt 7: 0 vin stable count number. vin_ov_cnt 7: 0 default : 0x0a access : r/w 70h vin_ov_cnt 7: 0 vin over-voltage count number. vin_uv_cnt 7: 0 default : 0x0a access : r/w 71h vin_uv_cnt 7: 0 vin under-voltage count number. vin_wrk_h_thrd 7: 0 default : 0xc3 access : r/w 72h vin_wrk_h_thrd 7: 0 vin working high threshold. vin_strtup_h_thr d 7: 0 default : 0xbb access : r/w 73h vin_strtup_h_thrd 7: 0 vin startup high threshold. vin_strtup_l_thr d 7: 0 default : 0x99 access : r/w 74h vin_strtup_l_thrd 7: 0 vin startup low threshold. vin_wrk_l_thrd 7: 0 default : 0x90 access : r/w 75h vin_wrk_l_thrd 7: 0 vin working low threshold. vin_wait_cnt_l 7: 0 default : 0xfa access : r/w 76h vin_wait_cnt[7:0] 7: 0 vin waiting count number (lower 8 bits). vin_wait_cnt_h 7: 0 default : 0x00 access : r/w - 7:4 reserved. 77h vinwait_cnt[11:8] 3: 0 vin waiting count number (upper 4 bits) when 6e[2] = 0, please refer to the following as register settings of 78h ~ 7bh: faultz_h_val 7: 0 default : 0xaa access : r/w 78h faultz_h_val[7:0] 7:0 faultz high boundary. faultz_l_val 7: 0 default : 0x55 access : r/w 79h faultz_l_val[7:0] 7:0 faultz low boundary. faultz_stb 7: 0 default : 0x0a access : r/w 7ah faultz_stb[7:0] 7:0 counts for faultz stable. faultz_dro p 7: 0 default : 0x0a access : r/w 7bh faultz_h_go_low 7:0 counts for faultz high go low. when 6e[2] = 1, please refer to the following as register settings of 78h ~ 7bh: mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 143 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description faultz_h_valu e 7: 0 default : 0xaa access : r/w 78h fb2_det_time[7:0] 7:0 fb2 detection time after burst high when system is in faultz high mode (lower 8 bits). faultz_l_valu e 7: 0 default : 0x55 access : r/w - 7:2 reserved. 79h fb2_detect_time[9:8] 1:0 fb2 detection time after burst high when system is in faultz high mode (higher 2 bits). faultz_stb_cnt 7: 0 default : 0x0a access : r/w 7ah fb2_det_fail_t 7:0 counts for fb2 failure is true. faultz_dro p 7: 0 default : 0x0a access : r/w 7bh fb2_l_faultz_h_md 7:0 fb2 low bound in faultz high mode. msur_ofst_ l 7: 0 default : 0x0e access : r/w 7ch msur_ofst[7:0] 7:0 measure offset time to get data (lower 8 bits). msur_ofst_h 7: 0 default : 0x00 access : r/w - 7:2 reserved. 7dh msur_ofst[9:8] 1:0 measure offset time to get data (higher 2 bits). 2us 7: 0 default : 0x48 access : r/w 7eh 2us_cnt 7:0 counts for 2us. 2us_msur 7: 0 default : 0x14 access : r/w 7fh 2us_msur 7:0 counts to get data when pwm on time 2us. fb1_com 7: 0 default : 0xaa access : ro 80h fb1_com[7:0] 7:0 fb1 command. fb2_strtup 7: 0 default : 0xaa access : r/w 81h fb2_strtup 7: 0 start-up fb2 command. fb2_set 7: 0 default : 0xaa access : r/w 82h fb2_set 7:0 fb2 command; adjust for continuous output adjusting. cont_ab 7: 0 default : 0xb7 access : r/w cont_a 7:4 a-value for continuous-mode. 83h cont_b 3:0 b-value for continuous-mode. brst_ab 7: 0 default : 0xb7 access : r/w brst_a 7:4 a-value for burst-mode. 84h brst_b 3:0 a-value for burst-mode. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 144 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description strk1_ l 7: 0 default : 0xa9 access : r/w 85h strk1_cnt[7:0] 7: 0 1 st ignition and normal operation count for pwm frequency; double buffer must fill-in from high to low. strk1_ h 7: 0 default : 0x00 access : r/w - 7:2 reserved. 86h strk1 [9:8] 1: 0 1 st ignition and normal operation count for pwm frequency; double buffer must fill-in from high to low. strk1_lmt_l 7: 0 default : - access : ro 87h strk1_lmt[7:0] 7:0 maximum duty for 1 st ignition and normal operation ; count for pwm frequency ( lower 8 bits). strk1_lmt_h 7: 0 default : - access : ro - 7:2 reserved. 88h strk1_lmt[9:8] 1:0 maximum duty for 1 st ignition and normal operation ; count for pwm frequency (higher 2 bits). strk2_ l 7: 0 default : 0xa9 access : r/w 89h strk2_cnt[7:0] 7: 0 2 nd ignition count for pwm frequency; double-buffer must fill-in from high to low (lower 8 bits). strk2_ h 7: 0 default : 0x00 access : r/w - 7:2 reserved. 8ah strk2 [9:8] 1: 0 2 nd ignition count for pwm frequency; double-buffer must fill-in from high to low (higher 2 bits). strk2_lmt 7: 0 default : - access : ro 8bh strk2_lmt[7:0] 7:0 maximum duty of 2 nd ignition; count for pwm frequency. strk2_lmt 7: 0 default : - access : ro - 7:2 reserved. 8ch strk2_lmt[9:8] 1:0 maximum duty for 2 nd ignition; count for pwm frequency. cnt_md 7: 0 default : 0x55 access : r/w fb2_md_ctrl 7:4 counts for entering fb2 mode control. 8dh faultz_ovp 3:0 counts for faultz over-voltage protection. brst_l 7: 0 default : 0x80 access : r/w 8eh brst_cnt[7:0] 7:0 counts for burst-mode frequency (lower 8 bits; filling sequence: 8fh, 8eh, 91h, 90h). 8fh brst_h 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 145 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description - 7:2 reserved. brst_cnt[9:8] 1:0 counts for burst-mode frequency (higher 2 bits; filling sequence: 8fh, 8eh, 91h, 90h). brst_duty_l 7: 0 default : 0x10 access : r/w 90h brst_duty[7:0] 7:0 counts for burst-mode duty (lower 8 bits; filling sequence: 8fh, 8eh, 91h, 90h). brst_duty_h 7: 0 default : 0x01 access : r/w - 7:2 reserved. 91h brst_duty[9:8 ] 1:0 counts for burst-mode duty (higher 2 bits; filling sequence: 8fh, 8eh, 91h, 90h). strk1_time_l 7: 0 default : 0x50 access : r/w 92h strk1_time[7:0] 7:0 counts for 1 st ignition time (lower 8 bits). strk1_time_m 7: 0 default : 0xc3 access : r/w 93h strk1_time[15:8] 7:0 counts for 1 st ignition time (middle 8 bits). strk1_time_h 7: 0 default : 0x00 access : r/w - 7:4 reserved. 94h strk1_time[19:16] 3:0 counts for 1 st ignition time (higher 4 bits). ttal_strk_time_l 7: 0 default : 0x38 access : r/w 95h ttal_strk_time[7:0] 7:0 counts for 1 st ignition time + 2 nd ignition time (lower 8 bits). ttal_strk_time_m 7: 0 default : 0xc1 access : r/w 96h ttal_strk_time[15:8] 7:0 counts for 1 st ignition time + 2 nd ignition time (middle 8 bits). ttal_strk_time_h 7: 0 default : 0x01 access : r/w - 7:4 reserved. 97h ttal_strk_time[19:16 ] 3:0 counts for 1 st ignition time + 2 nd ignition time (higher 4 bits). brst_ramp1 7: 0 default : 0x22 access : reserved 98h brst_ramp1[7:0] 7:0 burst-mode ramp control (lower 8 bits). brst_ramp2 7: 0 default : 0x11 access : reserved pwm_max_dut y 7 pwm maximum duty. 0: strike minus 16. 1: strike minus 32. steps 6:4 counts for steps. 99h brst_ramp1[11:8] 3:0 burst-mode ramp control (higher 4 bits). four steps: 99[3:1], {99[0], 98[7:6]}, 98[5:3], 98[2:0]. 9ah key_prtec 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 146 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description key_prtec 7: 0 key, code=cf. fail_stus 7: 0 default : - access : ro fail_safe_on 7 fail-safe finds pwm is over max-on time. faultz_h_md_fb2_f 6 faultz high-mode, fb2 fail. fb1_ovp 5 fb1 over-voltage protection while faultz is high. strk_fail 4 u nable to force faultz=1 after 2-step striking. faultz_abnrm 3 faultz accidentally goes from high to low. vin_ov 2 v in over-voltage. vin_uv 1 v in under-voltage. 9bh strtup_vin_f 0 s tartup vin fail. sar_fb2_dat 7: 0 default : - access : ro 9ch sar_fb2_dat 7: 0 sar fb2 data. sar_fb1_dat 7: 0 default : - access : ro 9dh sar_fb1_dat 7: 0 sar fb1 data. sar_faultz_dat 7: 0 default : - access : ro 9eh sar_faultz_dat 7: 0 sar faultz data. sar_vin_dat 7: 0 default : - access : ro 9fh sar_vin_dat 7: 0 sar vin data. duty_rprt1 7: 0 default : - access : ro a0h duty_rprt1[7:0] 7:0 pwm duty. duty_rprt2 7: 0 default : - access : ro a1h duty_rprt2[7:0] 7:0 pwm duty. duty_rprt3 7: 0 default : - access : ro - 7:4 reserved. a2h duty_rprt3[5:0] 5:0 pwm duty. sar_set1 7: 0 default : 0x09 access : r/w fs_q2_en 7 enable q2-fail safe. fs_q1_en 6 enable q1-fail safe. sar_clk_sel 5 se lect sar clock source. 0: pwm clock. 1: mpll_clk_out. a4h sar_clk_div_ratio 4:0 divide ratio for sar clock. a5h sar_set2 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 147 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description - 7:4 reserved. sar_ch_sel 3:2 channel select for sar. sar_debunce_set 1:0 de-bounce setting for sar. sar_set3 7: 0 default : 0x0b access : r/w a6h sar_sample_prd 7: 0 system clock counts for sample period. sar_set4 7: 0 default : 0x30 access : r/w c1_q2 7 se tting for programmable io. c1_q1 6 se tting for programmable io. c0_q2 5 se tting for programmable io. c0_q1 4 se tting for programmable io. epd_q2 3 enable input pad_q2 pull-down (default unused). epd_q1 2 enable input pad_q1 pull-down (default unused). en33v_dpwm 1 enable 3.3v supply for avdd_sar. a7h sar_tst 0 se t sar adc input to zero. hsync_pll_set 7: 0 default : 0x93 access : r/w use_clkdiv_en 7 enable bit for using clock divider instead of using pll. 0: disable. 1: enable. pll_lock 6 pll lock. strk1_sel 5 choose to use strike1 or synchronized strike1. clkin_sel 4 se lect to use mpll_clk_out/(mpll_clk_out/2). pll_mode 3:2 pll-mode setting. hsync_source_sel 1 se lect-bit for selecting the source of hsync. abh hsync_pll_en 0 enable bit for hsync pll. pll_cd 7: 0 default : 0x00 access : r/w pll_m_cd 7:4 pll m-code; must be>0. ach pll_n_cd 3:0 pll n-code; must be>0. pll_stus1 7: 0 default : - access : ro adh pll_stus_rprt 7: 0 hsync pll status report. pll_stus2 7: 0 default : - access : ro hsync_in 7 monitor input hsync. aeh pll_stus_rprt 6: 0 hsync pll status report. divd_ratio 7: 0 default : 0x30 access : r/w afh hsync_divd_ratio 7:0 divide-ratio while pll is in divider-mode. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 148 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. digital pwm register (bank = 04, registers 6bh ~ ffh) index name bits description wdt_l 7: 0 default : 0x00 access : r/w b0h wdt[7:0] 7:0 counts for wdt; (wanted pwm maximum on-time)/(biu clock) (lower 8 bits). wdt_h 7: 0 default : 0x00 access : r/w - 7:6 reserved. b1h wdt[9:8] 1:0 counts for wdt; (wanted pwm maximum on-time) / (biu clock) (higher 2 bits). pll_set 7: 0 default : 0x20 access : r/w - 7:6 reserved. hsync_safe_md 5 hs ync safe-mode. b2h pll_clmp_ratio 4:0 pll clamp value. - 7: 0 default : - access : - b3h ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 149 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) misc register (bank = 05) index name bits description - 7: 0 default : - access : - 00h ~ 09h - 7:1 reserved. reg_vd_10 7: 0 default : 0x69 access : r/w - 7:3 reserved. reg_lsctdis_e n 2 white peak detect bypass the coast signal enable. reg_premav_e n 1 first field macro-vision output enable. 10h reg_osdtst_e n 0 osd test pattern input adc path enable. - 7: 0 default : - access : - 11h ~ 1fh - 7:0 reserved. reg_calg 7: 0 default : 0x80 access : r/w reg_calg_en 7 0 : disable. 1: enable gain auto cal procedure. reg_calg_tri g 6 write an 1 to start gain cal procedure. reg_calg_upd 5 1 : auto update gain cal result. reg_calg_stssel 4 se lect gain cal status for cal status reg. reg_calg_ini 3: 2 select intrinsic adc gain for 0.7vpp input. 00: 0x6f. 01: 0x67. 10: 0x5f. 11: 0x57. reg_calo_blk 1 0 : use dout code 0 as offset cal target. 1: use dout code 16 (8-bit) as offset cal target. 20h reg_cal_lock 0 1 : ignode pll lock for cal. reg_gain_a gc0 7: 0 default : 0x80 access : r/w 21h reg_gain_agc 0 7:0 pga control for vd agc range 0. reg_gain_a gc1 7: 0 default : 0x80 access : r/w 22h reg_gain_agc 1 7:0 pga control for vd agc range 1. reg_gain_a gc2 7: 0 default : 0x80 access : r/w 23h reg_gain_agc 2 7:0 pga control for vd agc range 2. reg_adc_ov 7: 0 default : 0x80 access : r/w 24h reg_vref_ov 7 0 : disable. 1: enable adc vref override by register. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 150 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_gshift_o v 6 0: disable. 1: enable adc gshift override by register. reg_gain_ov 5 0 : disable. 1: enable adc gain override by register. reg_offset_o v 4 0: disable. 1: enable adc offset override by register. reg_agc_newmap 3 0 : disable. 1: enable pga controlled by register for vd agc. reg_gshift_agc 2: 0 gshift control for vd agc range 0,1,2 - 7: 0 default : - access : - 25h - 7:0 reserved. reg_adc_ictrl 7: 0 default : 0x05 access : r/w 26h reg_adc_ictrl 7:0 adc current control for pipeline stages. reg_adc 7: 0 default : 0x05 access : r/w reg_rdac_ictrl 7:6 adc r-dac current control. reg_adc_imode 5:4 adc current mode control. - 3 reserved. 27h reg_adc_vctrl 2:0 adc bias voltage control. reg_clamp 7: 0 default : 0x05 access : r/w - 7:6 reserved. reg_ref_tst 5:4 adc reference circuit test mode. 28h reg_vclamp_d 3: 0 select vd input clamp voltage level. - 7: 0 default : - access : - 29h - 7:0 reserved. reg_microcode_ 0_h 7: 0 default : 0x80 access : r/w 30h reg_microcode_0_h 7:0 microcode_0[15:8]. reg_gain_a gc1 7: 0 default : 0x80 access : r/w 31h reg_gain_agc 1 7:0 microcode_0[7:0]. reg_microcode_ 1_h 7: 0 default : 0x80 access : r/w 32h reg_microcode_1_h 7:0 microcode_1[15:8]. 33h reg_microcode_ 1_l 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 151 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_microcode_1_l 7:0 microcode_1[7:0]. reg_microcode_ 2_h 7: 0 default : 0x80 access : r/w 34h reg_microcode_2_h 7:0 microcode_2[15:8]. reg_microcode_ 2_l 7: 0 default : 0x80 access : r/w 35h reg_microcode_2_l 7:0 microcode_2[7:0]. reg_microcode_ 3_h 7: 0 default : 0x80 access : r/w 36h reg_microcode_ 3_h 7:0 microcode_3[15:8]. reg_microcode_ 3_l 7: 0 default : 0x80 access : r/w 37h reg_microcode_3_l 7:0 microcode_3[7:0]. reg_microcode_4 _h 7: 0 default : 0x80 access : r/w 38h reg_microcode_4_h 7:0 microcode_4[15:8]. reg_microcode_ 4_l 7: 0 default : 0x80 access : r/w 39h reg_microcode_4_l 7:0 microcode_4[7:0]. reg_microcode_ 5_h 7: 0 default : 0x80 access : r/w 3ah reg_microcode_5_h 7:0 microcode_5[15:8]. reg_microcode_5 _l 7: 0 default : 0x80 access : r/w 3bh reg_microcode_5_l 7:0 microcode_5[7:0]. reg_microcode_ 6_h 7: 0 default : 0x80 access : r/w 3ch reg_microcode_6_h 7:0 microcode_6[15:8]. reg_microcode_ 6_l 7: 0 default : 0x80 access : r/w 3dh reg_microcode_6_l 7:0 microcode_6[7:0]. reg_microcode_ 7_h 7: 0 default : 0x80 access : r/w 3eh reg_microcode_7_h 7:0 microcode_7[15:8]. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 152 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_microcode_ 7_l 7: 0 default : 0x80 access : r/w 3fh reg_microcode_7_l 7:0 microcode_7[7:0]. reg_microcode_ 8_h 7: 0 default : 0x80 access : r/w 40h reg_microcode_8_h 7:0 microcode_8[15:8]. reg_microcode_ 8_l 7: 0 default : 0x80 access : r/w 41h reg_microcode_8_l 7:0 microcode_8[7:0]. reg_microcode_ 9_h 7: 0 default : 0x80 access : r/w 42h reg_microcode_9_h 7:0 microcode_9[15:8]. reg_microcode_ 9_l 7: 0 default : 0x80 access : r/w 43h reg_microcode_9_l 7:0 microcode_9[7:0]. reg_microcode_ a_h 7: 0 default : 0x80 access : r/w 44h reg_microcode_a_h 7:0 microcode_a[15:8]. reg_microcode_ a_l 7: 0 default : 0x80 access : r/w 45h reg_microcode_a_l 7:0 microcode_a[7:0]. reg_microcode_ b_h 7: 0 default : 0x80 access : r/w 46h reg_microcode_b_h 7:0 microcode_b[15:8]. reg_microcode_ b_l 7: 0 default : 0x80 access : r/w 47h reg_microcode_b_l 7:0 microcode_b[7:0]. reg_microcode_ c_h 7: 0 default : 0x80 access : r/w 48h reg_microcode_c_h 7:0 microcode_c[15:8]. reg_microcode_ c_l 7: 0 default : 0x80 access : r/w 49h reg_microcode_c_l 7:0 microcode_c[7:0]. 4ah reg_microcode_ d_h 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 153 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_microcode_d_h 7:0 microcode_d[15:8]. reg_microcode_ d_l 7: 0 default : 0x80 access : r/w 4bh reg_microcode_d_l 7:0 microcode_d[7:0]. reg_microcode_ e_h 7: 0 default : 0x80 access : r/w 4ch reg_microcode_e_h 7:0 microcode_e[15:8]. reg_microcode_ e_l 7: 0 default : 0x80 access : r/w 4dh reg_microcode_e_l 7:0 microcode_e[7:0]. reg_microcode_ f_h 7: 0 default : 0x80 access : r/w 4eh reg_microcode_f_h 7:0 microcode_f[15:8]. reg_microcode_ f_l 7: 0 default : 0x80 access : r/w 4fh reg_microcode_f_l 7:0 microcode_f[7:0]. reg_bist 7: 0 default : 0x80 access : r - 7:2 reserved. any_bist_fail 1 any bist fail. 50h bist_done 0 bist done. reg_bist_en 7: 0 default : 0x80 access : r/w - 7:3 reserved. rstpatgen 2 reset pat gen. bist_en 1 bist enable. 51h bist_mode 0 bist mode. pattern[15:8] 7: 0 default : 0x80 access : r/w 52h pattern[15:8] 7:0 pattern[15:8]. pattern[7:0] 7: 0 default : 0x80 access : r/w 53h pattern[7:0] 7:0 pattern[7:0]. min_addr[15:8] 7: 0 default : 0x80 access : r/w 54h min_addr[15:8] 7:0 min_addr[15:8]. min_addr[7:0] 7: 0 default : 0x80 access : r/w 55h min_addr[7:0] 7:0 min_addr [7:0]. 56h max_addr[15:8] 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 154 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description max_addr[15:8] 7:0 max_addr [15:8]. max_addr[7:0] 7: 0 default : 0x80 access : r/w 57h max_addr[7:0] 7:0 max_addr [7:0]. retention_cntr [31:24] 7: 0 default : 0x80 access : r/w 58h retention_cntr [31:24] 7:0 retention_counter[31:24]. retention_cntr [23:16] 7: 0 default : 0x80 access : r/w 59h retention_cntr [23:16] 7:0 retention_counter[23:16]. retention_cntr [15:8] 7: 0 default : 0x80 access : r/w 5ah retention_cntr [15:8] 7:0 retention_counter[15:8]. retention_cntr [7:0] 7: 0 default : 0x80 access : r/w 5bh retention_cntr[7:0] 7:0 retention_counter[7:0]. bist_fail_bus [31:24] 7: 0 default : 0x80 access : r 5ch bist_fail_bus[31:24] 7:0 bist_fail_bus[31:24]. bist_fail_bus [23:16] 7: 0 default : 0x80 access : r 5dh bist_fail_bus[23:16] 7:0 bist_fail_bus[23:16]. bist_fail_bus [15:8] 7: 0 default : 0x80 access : r 5eh bist_fail_bus[15:8] 7:0 bist_fail_bus[15:8]. bist_fail_bus[7:0] 7: 0 default : 0x80 access : r 5fh bist_fail_bus[7:0] 7:0 bist_fail_bus[7:0]. reg_ip_vsyn c0 7: 0 default : 0x80 access : r/w 60h reg_ip_vsync 0 7:0 reg_ip_vsync0. reg_ip_vsyn c1 7: 0 default : 0x80 access : r/w 61h reg_ip_vsync 1 7:0 reg_ip_vsync1. reg_ip_sc0 7: 0 default : 0x80 access : r/w 62h reg_ip_sc0 7:0 reg_ip_sc0. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 155 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_ip_sc1 7: 0 default : 0x80 access : r/w 63h reg_ip_sc1 7:0 reg_ip_sc1. reg_ip_sc2 7: 0 default : 0x80 access : r 64h reg_ip_sc2 7:0 reg_ip_sc2. reg_ccfl_ 65 7: 0 default : 0x80 access : r/w 65h reg_ccfl_65 7:0 reg_ccfl_65. reg_ccfl_ 66 7: 0 default : 0x80 access : r/w 66h reg_ccfl_66 7:0 reg_ccfl_66. reg_osd_pad00_ 2nd 7: 0 default : 0x80 access : r/w 67h reg_osd_pad00_2nd 7:0 reg_osd_pad00_2nd. reg_osd_pad01_ 2nd 7: 0 default : 0x80 access : r/w 68h reg_osd_pad01_2nd 7:0 reg_osd_pad01_2nd. reg_osd_pad02_ 2nd 7: 0 default : 0x80 access : r/w 69h reg_osd_pad02_2nd 7:0 reg_osd_pad02_2nd. reg_osd_pad03_ 2nd 7: 0 default : 0x80 access : r/w 6ah reg_osd_pad03_2nd 7:0 reg_osd_pad03_2nd reg_osd_pad04_ 2nd 7: 0 default : 0x80 access : r/w 6bh reg_osd_pad04_2nd 7:0 reg_osd_pad04_2nd. reg_osd_pad05_ 2nd 7: 0 default : 0x80 access : r/w 6ch reg_osd_pad05_2nd 7:0 reg_osd_pad05_2nd. reg_osd_pad06_ 2nd 7: 0 default : 0x80 access : r/w 6dh reg_osd_pad06_2nd 7:0 reg_osd_pad06_2nd. reg_osd_pad07_ 2nd 7: 0 default : 0x80 access : r/w 6eh reg_osd_pad07_2nd 7:0 reg_osd_pad07_2nd. reg_osd_pad08_2 nd 7: 0 default : 0x80 access : r/w 6fh reg_osd_pad08_2nd 7:0 reg_osd_pad08_2nd. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 156 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_osd_pad09_ 2nd 7: 0 default : 0x80 access : r/w 70h reg_osd_pad09_2nd 7:0 reg_osd_pad09_2nd. reg_osd_pad0a_ 2nd 7: 0 default : 0x80 access : r/w 71h reg_osd_pad0a_2nd 7:0 reg_osd_pad0a_2nd. reg_osd_pad0b_ 2nd 7: 0 default : 0x80 access : r/w 72h reg_osd_pad0b_2nd 7:0 reg_osd_pad0b_2nd reg_osd_pad0c_ 2nd 7: 0 default : 0x80 access : r/w 73h reg_osd_pad0c_2nd 7:0 reg_osd_pad0c_2nd. reg_osd_pad0d_ 2nd 7: 0 default : 0x80 access : r 74h reg_osd_pad0d_2nd 7:0 reg_osd_pad0d_2nd. reg_osd_pad0e_ 2nd 7: 0 default : 0x80 access : r 75h reg_osd_pad0e_2nd 7:0 reg_osd_pad0e_2nd. reg_osd_pad0f_ 2nd 7: 0 default : 0x80 access : r 76h reg_osd_pad0f_2nd 7:0 reg_osd_pad0f_2nd. reg_osd_pad10_ 2nd 7: 0 default : 0x80 access : r 77h reg_osd_pad10_2nd 7:0 reg_osd_pad10_2nd. reg_osd_pad11_ 2nd 7: 0 default : 0x80 access : r/w 78h reg_osd_pad11_2nd 7:0 reg_osd_pad11_2nd. reg_osd_pad12_ 2nd 7: 0 default : 0x80 access : r/w 79h reg_osd_pad12_2nd 7:0 reg_osd_pad12_2nd. reg_osd_pad13_ 2nd 7: 0 default : 0x80 access : r/w 7ah reg_osd_pad13_2nd 7:0 reg_osd_pad13_2nd. 7bh reg_osd_pad14_ 2nd 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 157 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. misc register (bank = 05) index name bits description reg_osd_pad14_2nd 7:0 reg_osd_pad14_2nd. reg_osd_pad15_ 2nd 7: 0 default : 0x80 access : r/w 7ch reg_osd_pad15_2nd 7:0 reg_osd_pad15_2nd. reg_osd_pad16_ 2nd 7: 0 default : 0x80 access : r/w 7dh reg_osd_pad16_2nd 7:0 reg_osd_pad16_2nd. reg_osd_pad17_ 2nd 7: 0 default : 0x80 access : r/w 7eh reg_osd_pad17_2nd 7:0 reg_osd_pad17_2nd. reg_osd_def_ char_high_reg 7: 0 default : 0x80 access : r/w 7fh reg_osd_def_char_ high_reg 7:0 reg_osd_def_char_high_reg. reg_osd_cfont_ ext_start_adr 7: 0 default : 0x80 access : r/w 80h reg_osd_cfont_ext _start_adr 7:0 reg_osd_cfont_ext_start_adr. reg_osd_l_m8c_ ram_start 7: 0 default : 0x80 access : r/w 81h reg_osd_l_m8c_ram _start 7:0 reg_osd_l_m8c_ram_start. reg_pal32_ctrl 7: 0 default : 0x80 access : r/w 82h reg_pal32_ctrl 7:0 reg_pal32_ctrl. reg_op2_ctrl 7: 0 default : 0x80 access : r/w 83h reg_op2_ctrl 7:0 reg_osd_pad0a_2nd. reg_osc_set 7: 0 default : 0x80 access : r reg_bonding_ke y 7 bonding key status. - 6:3 reserved. reg_ring_osc_sel 2:1 ring-oscillator mode selection. 84h reg_ring_osc_e n 0 ring-oscillator enable. - 7: 0 default : - access : - 85h ~ ffh - 7:0 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 158 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) mgd register (bank = 05) index (absolute) mnemonic bit description reg0590 7:0 default : 0xff access : r/w 48h (0590h) histogram_thrd_0_l[7:0] 7:0 histogram threshold0 low byte. reg0591 7:0 default : 0xff access : r/w 48h (0591h) histogram_thrd_0_h[7:0] 7:0 histogram threshold0 high byte. reg0592 7:0 default : 0xff access : r/w 49h (0592h) histogram_thrd_1_l[7:0] 7:0 histogram threshold1 low byte. reg0593 7:0 default : 0xff access : r/w 49h (0593h) histogram_thrd_1_h[7:0] 7:0 histogram threshold1 high byte. reg0594 7:0 default : 0xff access : r/w 4ah (0594h) histogram_thrd_2_l[7:0] 7:0 histogram threshold2 low byte. reg0595 7:0 default : 0xff access : r/w 4ah (0595h) histogram_thrd_2_h[7:0] 7:0 histogram threshold2 high byte. reg0596 7:0 default : 0xff access : r/w 4bh (0596h) histogram_thrd_3_l[7:0] 7:0 histogram threshold3 low byte. reg0597 7:0 default : 0xff access : r/w 4bh (0597h) histogram_thrd_3_h[7:0] 7:0 histogram threshold3 high byte. reg0598 7:0 default : 0xf8 access : r/w fstable[3:0] 7:4 dcr power on control frame count. 4ch (0598h) yavg_alpha[3:0] 3:0 yavg frame alpha value, 0:current yavg, f:last yavg. reg0599 7:0 default : 0xfe access : r/w yavg_rgb_en 7 select rgb max value to calculate yavg, 0:select y for yavg. yavg_lim_en 6 enable yavg_avg to limit ygain tuning step. hist_rgb_en 5 se lect rgb max value to calculate histogram. hist_121_en 4 h istogram 121 low pass filter enable. yout_rgb_en 3 se lect rgb max value to lookup dlc gain. ygain_hist_lim_en 2 enable histogram to limit ygain max value. dlc_gain_lim_en 1 enable dlc gain limit function to keep detail of data. 4ch (0599h) dcr_en 0 enable dcr function. reg059a 7:0 default : 0x80 access : r/w 4dh (059ah) ygain[7:0] 7:0 gain for calculate ygain, 80->1x. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 159 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) index (absolute) mnemonic bit description reg059b 7:0 default : 0xa0 access : r/w 4dh (059bh) ygain_step[7:0] 7:0 ygain jump step. [7]: enable different of ygain for ygain step, [6:0]:gain of ydiff, 40 -> 1x. [6:0]:ygain step x2 when [7]=0. reg059c 7:0 default : 0x10 access : r/w 4eh (059ch) ygain_step_max[7:0] 7:0 max value of ygain jump step. reg059d 7:0 default : 0x01 access : r/w 4eh (059dh) ygain_step_min[7:0] 7:0 max value of ygain jump step. reg059e 7:0 default : 0x00 access : r/w 4fh (059eh) ygain_offset_l[7:0] 7:0 offset for calculate ygain, /16. reg059f 7:0 default : 0x00 access : r/w - 7:4 reserved. 4fh (059fh) ygain_offset_h[3:0] 3:0 offset for calculate ygain. reg05a0 7:0 default : 0x00 access : r/w 50h (05a0h) dlc_offset_l[7:0] 7:0 offset for calculate dlc gain, /16. reg05a1 7:0 default : 0x00 access : r/w - 7:4 reserved. 50h (05a1h) dlc_offset_h[3:0] 3:0 offset for calculate dlc gain, /16. reg05a2 7:0 default : 0x80 access : r/w 51h (05a2h) dlc_gain[7:0] 7:0 gain for calculate dlc gain, 80->1x. reg05a3 7:0 default : 0xff access : r/w 51h (05a3h) pwm_fdly[7:0] 7:0 pwm power on control. reg05a4 7:0 default : 0xff access : r/w 52h (05a4h) pwm_period_l[7:0] 7:0 pwm period set. reg05a5 7:0 default : 0xff access : r/w 52h (05a5h) pwm_period_h[7:0] 7:0 pwm period set. reg05a6 7:0 default : 0x00 access : r/w 53h (05a6h) pwm_duty_l[7:0] 7:0 pwm duty set. reg05a7 7:0 default : 0x00 access : r/w 53h (05a7h) pwm_duty_h[7:0] 7:0 pwm duty set. reg05a8 7:0 default : 0x00 access : r/w 54h (05a8h) pwm_r_offset_l[7:0] 7:0 offset for calculate pwm duty, /16. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 160 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) index (absolute) mnemonic bit description reg05a9 7:0 default : 0x00 access : r/w - 7:4 reserved. 54h (05a9h) pwm_r_offset_h[3:0] 3:0 offset for calculate pwm duty, /16. reg05aa 7:0 default : 0x00 access : r/w 55h (05aah) dcr_offset_l[7:0] 7:0 offset for calculate pwm duty gain, /16. reg05ab 7:0 default : 0x00 access : r/w - 7:4 reserved. 55h (05abh) dcr_offset_h[3:0] 3:0 offset for calculate pwm duty gain, /16. reg05ac 7:0 default : 0x80 access : r/w 56h (05ach) dcr_gain[7:0] 7:0 gain for calculate pwm duty gain, 80->1x. reg05ad 7:0 default : 0x10 access : r/w pwm_htotal_en 7 enable htotal for pwm period. pwm_inv 6 inverse pwm pol. pwm_rst_sel[1:0] 5:4 pwm reset select. 0: period. 1: vsync. 2: first line. 3: vertical blanking. dlc_en 3 enable dlc function. dlc_table_sel 2 dlc table debug mode enable. pwm_table_en 1 se lect dcr table for pwm control. 56h (05adh) - 0 reserved. reg05ae 7:0 default : 0x00 access : r/w 57h (05aeh) dlc_table_din[7:0] 7:0 dlc table debug din. reg05af 7:0 default : 0x00 access : r/w 57h (05afh) pwm_table_din[7:0] 7:0 pwm table debug din. reg05b0 7:0 default : 0x00 access : ro 58h (05b0h) yavg_out[7:0] 7:0 current frame y average. reg05b1 7:0 default : 0x00 access : ro 58h (05b1h) yavg_pre_out[7:0] 7:0 previous frame y average. reg05b2 7:0 default : 0x00 access : ro 59h (05b2h) yavg_avg_out[7:0] 7:0 current and previous y average by alpha. 59h reg05b3 7:0 default : 0x00 access : ro mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 161 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) index (absolute) mnemonic bit description (05b3h) ygain_out[7:0] 7:0 adjustment frame value. reg05b4 7:0 default : 0x00 access : ro 5ah (05b4h) ygain_tmp_out[7:0] 7:0 adjustment target frame value. reg05b5 7:0 default : 0x00 access : ro 5ah (05b5h) ygain_hist_out[7:0] 7:0 histogram frame value. reg05b6 7:0 default : 0x00 access : ro 5bh (05b6h) histogram0_l[7:0] 7:0 histogram result for sec0[7:0]. reg05b7 7:0 default : 0x00 access : ro 5bh (05b7h) histogram0_h[7:0] 7:0 histogram result for sec0[15:8]. reg05b8 7:0 default : 0x00 access : ro 5ch (05b8h) histogram1_l[7:0] 7:0 histogram result for sec1[7:0]. reg05b9 7:0 default : 0x00 access : ro 5ch (05b9h) histogram1_h[7:0] 7:0 histogram result for sec1[15:8]. reg05ba 7:0 default : 0x00 access : ro 5dh (05bah) histogram2_l[7:0] 7:0 histogram result for sec2[7:0]. reg05bb 7:0 default : 0x00 access : ro 5dh (05bbh) histogram2_h[7:0] 7:0 histogram result for sec2[15:8]. reg05bc 7:0 default : 0x00 access : ro 5eh (05bch) histogram3_l[7:0] 7:0 histogram result for sec3[7:0]. reg05bd 7:0 default : 0x00 access : ro 5eh (05bdh) histogram3_h[7:0] 7:0 histogram result for sec3[15:8]. reg05be 7:0 default : 0x00 access : ro 5fh (05beh) histogram4_l[7:0] 7:0 histogram result for sec4[7:0]. reg05bf 7:0 default : 0x00 access : ro 5fh (05bfh) histogram4_h[7:0] 7:0 histogram result for sec4[15:8]. reg05c0 7:0 default : 0x00 access : ro 60h (05c0h) histogram5_l[7:0] 7:0 histogram result for sec5[7:0]. reg05c1 7:0 default : 0x00 access : ro 60h (05c1h) histogram5_h[7:0] 7:0 histogram result for sec5[15:8]. reg05c2 7:0 default : 0x00 access : ro 61h (05c2h) histogram6_l[7:0] 7:0 histogram result for sec6[7:0]. reg05c3 7:0 default : 0x00 access : ro 61h (05c3h) histogram6_h[7:0] 7:0 histogram result for sec6[15:8]. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 162 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) index (absolute) mnemonic bit description reg05c4 7:0 default : 0x00 access : ro 62h (05c4h) histogram7_l[7:0] 7:0 histogram result for sec7[7:0]. reg05c5 7:0 default : 0x00 access : ro 62h (05c5h) histogram7_h[7:0] 7:0 histogram result for sec7[15:8]. reg05c6 7:0 default : 0x00 access : ro 63h (05c6h) histogram8_l[7:0] 7:0 histogram result for sec8[7:0]. reg05c7 7:0 default : 0x00 access : ro 63h (05c7h) histogram8_h[7:0] 7:0 histogram result for sec8[15:8]. reg05c8 7:0 default : 0x00 access : ro 64h (05c8h) histogram9_l[7:0] 7:0 histogram result for sec9[7:0]. reg05c9 7:0 default : 0x00 access : ro 64h (05c9h) histogram9_h[7:0] 7:0 histogram result for sec9[15:8]. reg05ca 7:0 default : 0x00 access : ro 65h (05cah) histogram10_l[7:0] 7:0 histogram result for sec10[7:0]. reg05cb 7:0 default : 0x00 access : ro 65h (05cbh) histogram10_h[7:0] 7:0 histogram result for sec10[15:8]. reg05cc 7:0 default : 0x00 access : ro 66h (05cch) histogram11_l[7:0] 7:0 histogram result for sec11[7:0]. reg05cd 7:0 default : 0x00 access : ro 66h (05cdh) histogram11_h[7:0] 7:0 histogram result for sec11[15:8]. reg05ce 7:0 default : 0x00 access : ro 67h (05ceh) histogram12_l[7:0] 7:0 histogram result for sec12[7:0]. reg05cf 7:0 default : 0x00 access : ro 67h (05cfh) histogram12_h[7:0] 7:0 histogram result for sec12[15:8]. reg05d0 7:0 default : 0x00 access : ro 68h (05d0h) histogram13_l[7:0] 7:0 histogram result for sec13[7:0]. reg05d1 7:0 default : 0x00 access : ro 68h (05d1h) histogram13_h[7:0] 7:0 histogram result for sec13[15:8]. reg05d2 7:0 default : 0x00 access : ro 69h (05d2h) histogram14_l[7:0] 7:0 histogram result for sec14[7:0]. reg05d3 7:0 default : 0x00 access : ro 69h (05d3h) histogram14_h[7:0] 7:0 histogram result for sec14[15:8]. 6ah reg05d4 7:0 default : 0x00 access : ro mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 163 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) index (absolute) mnemonic bit description (05d4h) histogram15_l[7:0] 7:0 histogram result for sec15[7:0]. reg05d5 7:0 default : 0x00 access : ro 6ah (05d5h) histogram15_h[7:0] 7:0 histogram result for sec15[15:8]. reg05d6 7:0 default : 0x00 access : r/w 6bh (05d6h) hact_l[7:0] 7:0 horizontal active pixel number[7:0]. reg05d7 7:0 default : 0x00 access : r/w - 7:4 reserved. 6bh (05d7h) hact_h[3:0] 3:0 horizontal active pixel number[11:8]. reg05d8 7:0 default : 0x00 access : r/w 6ch (05d8h) vact_l[7:0] 7:0 vertical active pixel number[7:0]. reg05d9 7:0 default : 0x00 access : r/w - 7:4 reserved. 6ch (05d9h) vact_h[3:0] 3:0 vertical active pixel number[11:8]. reg05da 7:0 default : 0x00 access : r/w 6dh (05dah) hblank[7:0] 7:0 horizontal blank position. reg05db 7:0 default : 0x00 access : r/w 6dh (05dbh) ygain_tmp_min[7:0] 7:0 ygain tmp min value. reg05dc 7:0 default : 0x00 access : ro 6eh (05dch) pwm_period_r[7:0] 7:0 pwm period output. reg05dd 7:0 default : 0x00 access : ro 6eh (05ddh) pwm_duty_r[7:0] 7:0 pwm duty output. reg05e0 7:0 default : 0x19 access : r/w vip_3d_dither_en 7 3 d dither enable. vip_3d_dither_obn8_en 6 3 d dither output bit number is 8 bits enable. 1: output 8 bits. 0: output 6 bits. vip_3d_dither_mono_en 5 3 d dither monochrome mode enable. vip_3d_dither_lsb_en 4 3 d dither lsb dither enable. vip_3d_dither_lsb_sel[1:0] 3:2 3d dither lsb dither table select. 70h (05e0h) vip_3d_dither_msb_sel[1:0] 1:0 3d dither msb dither table select. reg05e1 7:0 default : 0x00 access : r/w vip_3d_dither_on 7 3 d dither on. 70h (05e1h) vip_3d_dither_vclr_en 6 3 d dither vertical dither enable. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 164 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. mgd register (bank = 05) index (absolute) mnemonic bit description vip_3d_dither_vclr_no[1:0] 5:4 3d dither vertical dither table number. vip_3d_dither_lsb_vclr_e n 3 3d dither lsb vertical dither enable. vip_3d_dither_10_mod_e n 2 3d dither 10 mode detect enable. vip_3d_dither_lsb_vclr_no[1:0] 1:0 3d dither lsb vertical dither table number. reg05e2 7:0 default : 0x99 access : r/w vip_3d_dither_msb_r_mask[1:0] 7:6 3d dither msb r channel mask. vip_3d_dither_msb_b_mask[1:0] 5:4 3d dither msb b channel mask. vip_3d_dither_lsb_r_mask[1:0] 3:2 3d dither lsb r channel mask. 71h (05e2h) vip_3d_dither_lsb_b_mask[1:0] 1:0 3d dither lsb b channel mask. reg05e3 7:0 default : 0x0c access : r/w 71h (05e3h) vip_3d_dither_debug[7:0] 7:0 3d dither debug use. reg05e4 7:0 default : 0x27 access : r/w 72h (05e4h) h_dither_table0[7:0] 7:0 3d dither horizontal dither table0. reg05e5 7:0 default : 0x8d access : r/w 72h (05e5h) h_dither_table1[7:0] 7:0 3d dither horizontal dither table1. reg05e6 7:0 default : 0x63 access : r/w 73h (05e6h) h_dither_table2[7:0] 7:0 3d dither horizontal dither table2. reg05e7 7:0 default : 0x9c access : r/w 73h (05e7h) h_dither_table3[7:0] 7:0 3d dither horizontal dither table3. reg05e8 7:0 default : 0x4e access : r/w 74h (05e8h) v_dither_table0[7:0] 7:0 3d dither vertical dither table0. reg05e9 7:0 default : 0x4b access : r/w 74h (05e9h) v_dither_table1[7:0] 7:0 3d dither vertical dither table1. reg05ea 7:0 default : 0x93 access : r/w 75h (05eah) v_dither_table2[7:0] 7:0 3d dither vertical dither table2. reg05eb 7:0 default : 0x39 access : r/w 75h (05ebh) v_dither_table3[7:0] 7:0 3d dither vertical dither table3. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 165 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc registers (bank 06) adc_atop register (bank = 06) adc_atop register (bank = 06) index (absolute) mnemonic bit description reg0602 7:0 default : 0x00 access : r/w - 7:3 reserved. vd_yc_en 2 1: enable s-video input function. vd_en 1 1: enable vd function. 01h (0602h) adc_ena 0 1: enable adc_a rgb function. reg0604 7:0 default : 0x00 access : r/w mux_bsel[1:0] 7:6 badc mux sel, 00:rgb/ypbpr , 01:vd ,10:dvi,11:reserved. mux_gsel[1:0] 5:4 gadc mux sel, 00:rgb/ypbpr , 01:vd ,10:dvi,11:reserved. mux_rsel[1:0] 3:2 radc mux sel, 00:rgb/ypbpr , 01:vd ,10:dvi,11:reserved. 02h (0604h) amuxa[1:0] 1:0 select adc_a rgb channel, vd fb mode rgb channel. 00: selects input channel 0. 01: selects input channel 1. 10: selects input channel 2. reg0605 7:0 default : 0x40 access : r/w - 7 reserved. mux_rgb_en 6 1: enable rgb mux. mux_rgbsel[1:0] 5:4 00: channel0 , 01:channel1, 10:channel2. 02h (0605h) - 3:0 reserved. reg0606 7:0 default : 0x00 access : r/w 03h (0606h) mux_vdsel_c[3:0] 7:4 select vd sc channel. 0000: cvbs0. 0001: cvbs1. 0010: cvbs2. 0011: cvbs3. 0100: cvbs4 (y0). 0101: cvbs5 (y1). 0110: cvbs6 (c0). 0111: cvbs7 (c1). 1000: r0. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 166 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description 1001: r1. 1010: r2. others: none. mux_vdsel_y[3:0] 3:0 select vd cvbs/y channel. 0000: cvbs0. 0001: cvbs1. 0010: cvbs2. 0011: cvbs3. 0100: cvbs4 (y0). 0101: cvbs5 (y1). 0110: cvbs6 (c0). 0111: cvbs7 (c1). 1000: g0. 1001: g1. 1010: g2. others: none. reg0607 7:0 default : 0x00 access : r/w - 7:6 reserved. test_clkmux_rgb_inv 5 1: invert rgb adc clock phase. - 4 reserved. mux_rgbvd 3 1: rgb adc in vd mode. - 2 reserved. mux_c_en 1 1: enable vd-c channel mux. 03h (0607h) mux_y_en 0 1: enable vd-y channel mux. reg0608 7:0 default : 0xff access : r/w pdn_pll 7 1: power down adc pll. pdn_phd 6 1: power down phase digitizer. pdn_adcb 5 1: power down adc_b. pdn_adcg 4 1: power down adc_g. pdn_adcr 3 1: power down adc_r. pdn_ref 2 1: power down all reference voltage. pdn_bg 1 1: power down bandgap. 04h (0608h) pdn_ref_rgb 0 1: power down rgb adc reference voltage. reg0609 7:0 default : 0x7f access : r/w 04h (0609h) - 7 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 167 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description pdn_hsync 6 1: power down hsync_cmp. pdn_sog_main 5 1: power down online sog main. pdn_sog_dac 4 1: power down online sog dac. pdn_pll2 3 1: power down vd pll. pdn_iclp_vdc 2 1: power down i-clamp on vd-c channel. pdn_iclp_vdy 1 1: power down i-clamp on vd-y channel. pdn_iclp_rgb 0 1: power down i-clamp on rgb channel. reg060a 7:0 default : 0x07 access : r/w - 7:3 reserved. pdn_adcpla_pdac_b 2 1= power down adcpla phase dac b. pdn_adcpla_pdac_g 1 1= power down adcpla phase dac g. 05h (060ah) pdn_adcpla_pdac_r 0 1= power down adcpla phase dac r. reg060c 7:0 default : 0xff access : r/w 06h (060ch) pd_clk[7:0] 7:0 clock power down control. [0]: pd_clkxtal. [1]: pd_clk200. [2]: pd_clk400. [3]: pd_clkpll. [4]: pd_clkd_r. [5]: pd_clkd_g. [6]: pd_clkd_b. [8]: pd_clkd. [9]: pd_clkd_vd. [10]: pd_dvidetclk. reg060d 7:0 default : 0xff access : r/w 06h (060dh) pd_clk[15:8] 7:0 see description of '060ch'. reg060e 7:0 default : 0x00 access : r/w 07h (060eh) softrst[7:0] 7:0 1: soft reset for adcpll blocks. [15:6]: reserved. [5]: soft-reset phase dac. [4]: soft-reset atop. [3]: soft-reset pllb. [2]: soft-reset adcb. [1]: soft-reset plla. [0]: soft-reset adca. 07h reg060f 7:0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 168 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description (060fh) softrst[15:8] 7:0 see description of '060eh'. reg0612 7:0 default : 0x00 access : r/w - 7:5 reserved. adc_pll_porst_en 4 pull the lpf of the pll to zero. 1: zero. 0: normal. 09h (0612h) - 3:0 reserved. reg0613 7:0 default : 0x00 access : r/w - 7:5 reserved. vd_pll_porst_en 4 pull the lpf of the pll to zero. 1: zero. 0: normal. 09h (0613h) - 3:0 reserved. reg0614 7:0 default : 0xc1 access : r/w - 7:5 reserved. adc_pll_mod[1:0] 4:3 select the divider number of the post divider. 00: normal; 01: div2; 10:div4; 11:div8. 0ah (0614h) adc_pll_mult[2:0] 2:0 adc pll clock multiplier = n+1. 000: /1. 001: /2. &&. 111: /8. reg0615 7:0 default : 0xc1 access : r/w - 7:5 reserved. vd_pll_mod[1:0] 4:3 select the divider number of the post divider. 00: normal; 01: div2; 10:div4; 11:div8. 0ah (0615h) vd_pll_mult[2:0] 2:0 adc pll clock multiplier = n+1. 000: /1. 001: /2. &&. 111: /8. - 7:0 default : - access : - 0bh ~ 0dh (0616h ~ 061bh) - - reserved. 0fh reg061e 7:0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 169 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description (061eh) adcpla_phase_cc[7:0] 7:0 select adca sampling clock phase. reg061f 7:0 default : 0x00 access : r/w - 7:2 reserved. 0fh (061fh) adcpla_phase_cc[9:8] 1:0 see description of '061eh'. reg0620 7:0 default : 0x1f access : r/w 10h (0620h) adcpla_phase_delta[7:0] 7:0 select adca phase delta between clkcc & clkadc. reg0621 7:0 default : 0x00 access : r/w - 7:2 reserved. 10h (0621h) adcpla_phase_delta[9:8] 1:0 see description of '0620h'. - 7:0 default : - access : - 11h ~ 12h (0622h ~ 0624h) - - reserved. - 7:0 default : - access : - 13h ~ 17h (0626h ~ 062eh) - - reserved. reg0630 7:0 default : 0x00 access : r/w - 7:2 reserved. adcpla_plldiv_dbload_wait_vsync 1 1 = update plldiv during phase vsync. 18h (0630h) adcpla_phase_dbload_wait_vsync 0 1 = update phase during phase vsync. - 7:0 default : - access : - 18h ~ 19h (0631h ~ 0633h) - - reserved. reg0640 7:0 default : 0x00 access : r/w - 7:3 reserved. 20h (0640h) hsync_lvl[2:0] 2:0 select hsync cmp's reference voltage. 000: refh=1.54v, refl=1.10v. 001: refh=1.54v, refl=0.88v. 010: refh=1.76v, refl=1.10v. 011: refh=1.76v, refl=0.88v. 100: refh=1.87v, refl=1.10v. 101: refh=1.87v, refl=0.88v. 110: refh=1.76v, refl=1.32v. 111: refh=1.87v, refl=1.32v. 21h ~ 21h - 7:0 default : - access : - mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 170 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description (0642h ~ 0643h) - - reserved. reg0644 7:0 default : 0x30 access : r/w 22h (0644h) xtal_freq[7:0] 7:0 set xtal frequency for timing detection normalization (default: 12mhz, format: 6.2 mhz). reg0645 7:0 default : 0x00 access : r/w - 7:2 reserved. adc_inmsel 1 1: enable one negative pin function. 22h (0645h) - 0 reserved. reg0646 7:0 default : 0x00 access : r/w - 7:6 reserved. ydit_md[2:0] 5:3 select adc y dither mode for display. 23h (0646h) cdit_md[2:0] 2:0 select adc c dither mode. 000: off. 001: 1-bit noise. 010: 2-bit noise. 011: 3-bit noise. 100: seq2 1-bit toggle noise. 101: seq2 2-bit toggle noise. 110: seq4 2-bit toggle noise. 110: seq4 3-bit toggle noise. - 7:0 default : - access : - 23h (0647h) - - reserved. reg0648 7:0 default : 0x00 access : r/w blpf_bwm[3:0] 7:4 b-channel negative input lpf bandwidth. 24h (0648h) blpf_bwp[3:0] 3:0 b-channel positive input lpf bandwidth. reg0649 7:0 default : 0x00 access : r/w glpf_bwm[3:0] 7:4 g-channel negative input lpf bandwidth. 24h (0649h) glpf_bwp[3:0] 3:0 g-channel positive input lpf bandwidth. reg064a 7:0 default : 0x00 access : r/w rlpf_bwm[3:0] 7:4 r-channel negative input lpf bandwidth. 25h (064ah) rlpf_bwp[3:0] 3:0 r-channel positive input lpf bandwidth. - 7:0 default : - access : - 25h ~ 27h (064bh ~ 064eh) - - reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 171 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description reg0650 7:0 default : 0x00 access : r/w - 7:6 reserved. vdlpfgain_c 5 1: gain=2 in vd-c lpf. vdlpfgain_y 4 1: gain=2 in vd-y lpf. - 3:2 reserved. vlpf_c_en 1 1: enable vd-c lpf. 28h (0650h) vlpf_y_en 0 1: enable vd-y lpf. - 7:0 default : - access : - 28h (0651h) - - reserved. reg0652 7:0 default : 0x00 access : r/w - 7:5 reserved. 29h (0652h) sog_bw[4:0] 4:0 select online sog filter bandwidth. 00000: 973mhz. 00001: 116mhz. 00011: 63mhz. 00111: 43mhz. 01111: 32mhz. 11111: 26mhz. reg0653 7:0 default : 0x00 access : r/w - 7:6 reserved. sog_cal_en 5 for rising edge trigger enable of sog online calibration 0->1. sog_hys 4 [0]: disable online sog comparator hysteresis function. sog_cal 3 [0]: enable online sog calibration loop. 29h (0653h) - 2:0 reserved. reg0654 7:0 default : 0x00 access : r/w sog_vclp[3:0] 7:4 [0]: select online sog clamping voltage. xxx0: 1.11v. xxx1: 1.2v. 2ah (0654h) sog_sw[3:0] 3:0 select online sog input source. xx00: sogin0. xx01: sogin1. xx10: sogin2. xx11: sogin3. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 172 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description reg0656 7:0 default : 0x20 access : r/w 2bh (0656h) sog_vcomp[7:0] 7:0 [7:0] : select online sog comparator threshold voltage. =1.08+(1.32-1.08)/256*codes. . [11:10] select online sog comparator hysteresis voltage. 00: 5mv. 01: 10mv. 10: 15mv. 11: 20mv. reg0657 7:0 default : 0x00 access : r/w - 7:4 reserved. 2bh (0657h) sog_vcomp[11:8] 3:0 see description of '0656h'. reg0658 7:0 default : 0x05 access : r/w - 7:3 reserved. sog_control_offset 2 1=add user offset for offset code on online. sog_control_bypass 1 1= bypass online sog control register. 2ch (0658h) pdn_sog_mux 0 1: power down online sog mux. reg065a 7:0 default : 0x20 access : r/w 2dh (065ah) sog_init_wait_time[7:0] 7:0 sog online calibration initial setup waiting time. reg065b 7:0 default : 0x10 access : r/w 2dh (065bh) sog_sweep_wait_time[7:0] 7:0 sog online calibration sweep code waiting time. reg065c 7:0 default : 0x08 access : r/w 2eh (065ch) sog_eva_wait_time[7:0] 7:0 sog online calibration evaluate code waiting time. reg065e 7:0 default : 0x00 access : ro 2fh (065eh) sog_status[7:0] 7:0 sog online calibration function test status. {sog,cal_en,sog_vcomp}. reg065f 7:0 default : 0x00 access : ro - 7:2 reserved. 2fh (065fh) sog_status[9:8] 1:0 see description of '065eh'. reg0668 7:0 default : 0x00 access : r/w - 7:4 reserved. 34h (0668h) trim_ldo_rgb_sel 3 1: vcal from ldo rstring for rgb 0: vcal from trimming for rgb. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 173 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description ldo_rgb_sel 2 1: 1.05v output voltage from ldo rstring for rgb. 0: 0.55v output votlage from ldo rstring for rgb. vbg_en 1 ldo_en 0 1: enable 1.05v and 0.55v output from ldo rstring 0:disable. - 7:0 default : - access : - 34h ~ 39h (0669h ~ 0673h) - - reserved. - 7:0 default : - access : - 40h (0680h) - - reserved. - 7:0 default : - access : - 41h ~ 44h (0682h ~ 0689h) - - reserved. reg068a 7:0 default : 0x01 access : r/w - 7:2 reserved. 45h (068ah) hs_adc_sel_mux[1:0] 1:0 clkd_atop select, 00/01/10/11: r/g/b/r. - 7:0 default : - access : - 45h ~ 47h (068bh ~ 068fh) - - reserved. - 7:0 default : - access : - 4ah ~ 4dh (0694h ~ 069bh) - - reserved. reg069e 7:0 default : 0x00 access : r/w 4fh (069eh) hsync_deglitch_th[7:0] 7:0 select hsync deglitch pulse width threshold (step size = mpll clock). reg069f 7:0 default : 0x00 access : r/w 4fh (069fh) sog_deglitch_th[7:0] 7:0 select sog deglitch pulse width threshold (step size = mpll clock). reg06a0 7:0 default : 0x00 access : r/w - 7:6 reserved. ip_sog_deglitch 5 1: enable sog input deglitch for ip mode detection. 50h (06a0h) ip_hsync_deglitch 4 1: enable hsync input deglitch for ip mode detection. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 174 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description pll_sog_deglitch 3 1: enable sog input deglitch for pll. pll_hsync_deglitch 2 1: enable hsync input deglitch for pll. adc_sog_deglitch 1 1: enable sog input deglitch for adc clamp. adc_hsync_deglitch 0 1: enable hsync input deglitch for adc clamp. - 7:0 default : - access : - 60h (06c0h) - - reserved. - 7:0 default : - access : - 61h ~ 61h (06c2h ~ 06c3h) - - reserved. reg06e0 7:0 default : 0x01 access : r/w - 7:3 reserved. mpll_clk_adc216m_pd 2 1: disable mpll_clk_adc216m clock ou. mpll_clk_adc432m_pd 1 1: disable mpll_clk_adc432m clock ou. 70h (06e0h) mpll_pd 0 1: power down mplll. reg06e2 7:0 default : 0x00 access : r/w - 7:2 reserved. mpll_disfrun 1 disable vco free-run. 71h (06e2h) mpll_in_select 0 input clock selection:. while test[5]=1'b1,. 1'b0 1.0v clock input;. 1'b1 3.3v clock input after internal level shift to 1.0v;. - 7:0 default : - access : - 71h (06e3h) - - reserved. reg06e4 7:0 default : 0x04 access : r/w - 7:4 reserved. mpll_output_div[1:0] 3:2 output-divider control:. 2'b00: /1;. 2'b01: /2; <-- default. 2'b10: /4;. 2'b11: /8:. 72h (06e4h) mpll_input_div[1:0] 1:0 input-divider control:. 2'b00: /1; <-- default. 2'b01: /2;. 2'b10: /4;. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 175 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_atop register (bank = 06) index (absolute) mnemonic bit description 2'b11: /8:. reg06e5 7:0 default : 0x12 access : r/w - 7:5 reserved. 72h (06e5h) mpll_loop_div[4:0] 4:0 loop-divider control:. 5'h00: /1; 5'h01: /1; 5'h02: /2; 5'h03: /3 &. 5'h1f: /31;. others are not acceptable;. reg06e6 7:0 default : 0x00 access : r/w - 7:2 reserved. 73h (06e6h) mpll_icp_ictrl[1:0] 1:0 charge-pump current control:. 2'h00: icp x 4. 2'h01: icp x 3. 2'h10: icp x 2. 2'h11: icp x1. reg06e8 7:0 default : 0x31 access : r/w - 7:6 reserved. xtal_sel[1:0] 5:4 xtal gain control. - 3:1 reserved. 74h (06e8h) xtal_en 0 xtal enable control (active high). - 7:0 default : - access : - 75h ~ 77h (06eah ~ 06efh) - - reserved. - 7:0 default : - access : - 7fh ~ 7fh (06feh ~ 06ffh) - - reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 176 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) adc_dtop register (bank = 06) index (absolute) mnemonic bit description reg0602 7: 0 default : 0x95 access : r/w 01h (0602h) plldiv[7:0] 7:0 adc pll divider ratio (htotal-3). (write sequence lsb -> msb). reg0603 7: 0 default : 0x06 access : r/w - 7:5 reserved. 01h (0603h) plldiv[12:8] 4: 0 see description of '0602h'. reg0604 7: 0 default : 0x82 access : r/w 02h (0604h) bwcoef[7:0] 7:0 adc pll bandwidth coefficient. reg0605 7: 0 default : 0x09 access : r/w 02h (0605h) freqcoef[7:0] 7:0 adc pll frequency coefficient. reg0606 7: 0 default : 0x05 access : r/w 03h (0606h) dampcoef[7:0] 7:0 adc pll damping coefficient. - 7: 0 default : - access : - 03h (0607h) - - reserved. reg0608 7: 0 default : 0x05 access : r/w pll_status_sel[2:0] 7: 5 select pll digital status. phd_cal_dis 4 disable phase digitalizer calibration. 04h (0608h) settle_cnt[3:0] 3: 0 select phase digitalizer settling time. reg0609 7: 0 default : 0xc6 access : r/w wdog_tol[1:0] 7: 6 select pll watch dog reset tolerance. iqclr_th[2:0] 5:3 pll lock to unlock threshold. 04h (0609h) iqset_th[2:0] 2:0 pll unlock to lock threshold. reg060a 7: 0 default : 0x00 access : ro 05h (060ah) pll_status[7:0] 7:0 pll digital status. 000: {lock, iq, slow, fast, freerun, 3'b000}. - 7: 0 default : - access : - 06h ~ 06h (060ch ~ 060dh) - - reserved. reg060e 7: 0 default : 0x8a access : r/w hsync_pol 7 input hsync polarity. 0: low active. 1: high active. 07h (060eh) sog_en 6 se lect pll locking source. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 177 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description 0: hsync. 1: sog. hsync_edge 5 se lect pll locking edge. 0: hsync leading edge. 1: hsync trailing edge. clamp_edge 4 se lect clamp reference edge. 0: hsync trailing edge. 1: hsync leading edge. ccdis 3 1 : disable clamp during coast region. wdog_dis 2 1 : disable adc pll watch dog. coast_pol 1 se lect coast polarity. 0: low active. 1: high active. - 0 reserved. reg060f 7: 0 default : 0x00 access : r/w 07h (060fh) hsout_pw[7:0] 7: 0 select extended hsout pulse width. reg0611 7: 0 default : 0x05 access : r/w 08h (0611h) clamp_dur[7:0] 7: 0 select clamp pulse duration. reg0612 7: 0 default : 0x00 access : r/w - 7:2 reserved. hsout_gen 1 1 : enable hsout pulse extension. 09h (0612h) - 0 reserved. - 7: 0 default : - access : - 09h (0613h) - - reserved. reg0616 7: 0 default : 0x40 access : r/w 0bh (0616h) timeout_h[7:0] 7: 0 hsync activity timeout period (100us). reg0617 7: 0 default : 0x64 access : r/w 0bh (0617h) timeout_v[7:0] 7: 0 vsync activity timeout period (ms). reg0618 7: 0 default : 0x00 access : ro - 7:6 reserved. 0ch (0618h) ovf_rgb[5:0] 5:0 adc overflow flags, { ovfb, unfb, ovfg, unfg, ovfr, unfr}. reg0619 7: 0 default : 0x00 access : ro, wo 0ch (0619h) - 7:4 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 178 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description sog_tog 3 1 : active channel sog toggle status. vsync_tog 2 1 : active channel vsync toggle status. hsync_tog 1 1 : active channel hsync toggle status. clrovf_rgb 0 write a 1 to clear adc_rgb overflow flags. reg061a 7: 0 default : 0x05 access : r/w 0dh (061ah) clamp_dly[7:0] 7: 0 select clamp pulse start position relative to input hsync edge. reg061b 7: 0 default : 0x00 access : r/w - 7:6 reserved. vclamp_en_hact 5 1 : enable hact window. vclamp_hsync_or_hsout 4 0 : use hsync, 1: use hsout. 0dh (061bh) clamp_dly[11:8] 3: 0 see description of '061ah'. reg0620 7: 0 default : 0x24 access : r/w - 7:6 reserved. 10h (0620h) rgb_swap[5:0] 5: 0 select rgby data to scalar. [1:0]: sel r. [3:2]: sel g. [5:4]: sel b. 00: r. 01: g. 10: b. 11: blank. reg0624 7: 0 default : 0x00 access : r/w - 7:6 reserved. bmida[1:0] 5: 4 0/1=select gnd-clamp/mid-clamp for adc b. 00: 10h000. 01: 10h040. 10: 10h200. gmida[1:0] 3: 2 0/1=select gnd-clamp/mid-clamp for adc g. 00: 10h000. 01: 10h040. 10: 10h200. 12h (0624h) rmida[1:0] 1: 0 0/1=select gnd-clamp/mid-clamp for adc r. 00: 10h000. 01: 10h040. 10: 10h200. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 179 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description reg0625 7: 0 default : 0x28 access : r/w - 7:6 reserved. hsout2sc_pipedly[3:0] 5: 2 hsout pipe delay 1~16=0~f. sync_sel_yuv 1 y uv sync sel 1:vd 0:scalar. 12h (0625h) sync_sel_rgb 0 rgb sync sel 1:vd 0:scalar. reg0626 7: 0 default : 0x84 access : r/w - 7:3 reserved. 13h (0626h) dit_disp[2:0] 2: 0 select adc rgb dither mode for display. - 7: 0 default : - access : - 13h (0627h) - - reserved. reg0628 7: 0 default : 0x28 access : r/w 14h (0628h) vssep_th[7:0] 7: 0 select vsync separator threshold width (unit=xtal period*2). reg0629 7: 0 default : 0x40 access : r/w - 7 reserved. cal_bw 6 1 : enable max adc bandwidth during cal. sync_sel 5 se lect sync source for adc_dig. 0: from scalar. 1: from adc sync process block. coast_en 4 enable coast generator. 0: disable coast. 1: enable coast. coast_hs 3 se lect hsync sources for coast line counter. 0: pll locked hsout. 1: input hsync. vsync_pol 2 input vsync polarity. 0: low active. 1: high active. vs_sel 1 se lect vsync input source. 0: vsync. 1: separated vsync. 14h (0629h) vssep_sel 0 se lect vsync separator input source. 0: hsync or sog. 1: vsync. 15h reg062a 7: 0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 180 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description (062ah) precoast[7:0] 7: 0 select precoast lines before vsync. reg062b 7: 0 default : 0x00 access : r/w 15h (062bh) postcoast[7:0] 7: 0 select postcoast lines after vsync. reg062c 7: 0 default : 0x00 access : r/w - 7:3 reserved. 16h (062ch) lat_sync_dly_sel[2:0] 2: 0 select postcoast lines after vsync. reg062e 7: 0 default : 0x14 access : r/w 17h (062eh) iclamp_clpdly[7:0] 7:0 register setting for delay. (to start of analog clamp). reg062f 7: 0 default : 0x00 access : r/w - 7:4 reserved. 17h (062fh) iclamp_clpdly[11:8] 3: 0 see description of '062eh'. reg0630 7: 0 default : 0x08 access : r/w 18h (0630h) iclamp_caldur[7:0] 7:0 register setting for duration, only for 2^n. (of analog clamp). reg0631 7: 0 default : 0x04 access : r/w - 7:4 reserved. iclamp_ven 3 1 =enable clamp once every vsync. iclamp_coast_clp_di s 2 1 = disable clamp during coast region (synced). iclamp_hsync_or_hsout 1 0 : use hsync, 1: use hsout. 18h (0631h) iclamp_clp_edge 0 1 : raising edge, 0:falling edge. reg0632 7: 0 default : 0x00 access : r/w 19h (0632h) iclamp_vdly[7:0] 7:0 clamp pulse line delay for vsync mode. reg0633 7: 0 default : 0x00 access : r/w iclamp_clk_rate_in 7 analog iclamp clk polarity, 0:pass, 1:inverit. iclamp_clk_rate[1:0] 6: 5 00: x1 analog iclamp. 01: x2. 10: x4. 11: x4. iclamp_coast_ext_cnt[2:0] 4:2 coast extend 0~7 line option. iclamp_en_coast_ext_cnt 1 1 : enable coast extend 0~7 line option. 19h (0633h) iclamp_en_hact 0 1 : enable hact window. 1bh reg0636 7: 0 default : 0x80 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 181 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description (0636h) iclamp_r_blank_lvl[7:0] 7:0 blanking level = 128 (rgb). reg0637 7: 0 default : 0x00 access : r/w - 7:4 reserved. 1bh (0637h) iclamp_r_blank_lvl[11:8] 3: 0 see description of '0636h'. reg0638 7: 0 default : 0x05 access : r/w 1ch (0638h) iclamp_r_lock_level[7:0] 7:0 lock level threshold. reg0639 7: 0 default : 0x00 access : r/w - 7:4 reserved. 1ch (0639h) iclamp_r_lock_level[11:8] 3: 0 see description of '0638h'. reg063a 7: 0 default : 0xd0 access : r/w 1dh (063ah) iclamp_r_lock_cnt[7:0] 7:0 match reg_iclamp_lock_level counter. reg063b 7: 0 default : 0x07 access : r/w - 7:5 reserved. 1dh (063bh) iclamp_r_lock_cnt[12:8] 4: 0 see description of '063ah'. reg063c 7: 0 default : 0x60 access : r/w iclamp_r_k1_stb[0] 7 k1 = 2^(clmp_k1[6:3]-8-2) * (1 + clmp_k1[2:0]/8). for stable. 1eh (063ch) iclamp_r_k1_ini[6:0] 6: 0 k1 = 2^(clmp_k1[6:3]-8-2) * (1 + clmp_k1[2:0]/8). for initial. reg063d 7: 0 default : 0x20 access : r/w - 7:6 reserved. 1eh (063dh) iclamp_r_k1_stb[6:1] 5: 0 see description of '063ch'. reg063e 7: 0 default : 0xa0 access : r/w iclamp_r_k1_en 7 clamping = leakage + err * gain_true * k1 * k1_en;. 1fh (063eh) iclamp_r_k2[6:0] 6: 0 k2 = 2^(clmp_k2[6:3]-8) * (1 + clmp_k2[2:0]/8);. reg063f 7: 0 default : 0x03 access : r/w - 7:5 reserved. iclamp_r_frez_clmp[2:0] 4:2 clamping = leakage. leakage is frozen. (coast). k1_en = 0 and k2_en = 0. frez_clmp = frez_clmp_1 | frez_clmp_2 | frez_clmp_3;. 1fh (063fh) iclamp_r_type 1 0 : bottom clamping, rgb/ypbpr = 0;. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 182 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description 1: back-porch calmping. iclamp_r_k2_en 0 leakage = leakage + err * gain_true * k1 * k2 * k2_en;. reg0640 7: 0 default : 0x00 access : r/w 20h (0640h) iclamp_r_agc_fine[7:0] 7:0 agc fine gain. reg0641 7: 0 default : 0x1c access : r/w - 7:6 reserved. iclamp_r_agc_coarse[1:0] 5:4 agc coarse gain. 20h (0641h) iclamp_r_agc_fine[11:8] 3: 0 see description of '0640h'. reg0642 7: 0 default : 0x40 access : r/w 21h (0642h) iclamp_r_pga_ofst[7:0] 7:0 pga offset. reg0643 7: 0 default : 0x05 access : r/w - 7:5 reserved. 21h (0643h) iclamp_r_err_max[4:0] 4:0 bac_porch_level error < +- reg_clmp_err_max <= +-31 * 8 !!!. reg0644 7: 0 default : 0x4a access : r/w iclamp_r_lkg_mode[1:0] 7: 6 001: adaptive leakage tracking. 001: adaptive leakage tracking. leakage is bounded by +- reg_iclamp_lkg[4:0]. 010: freeze leakage. 011: load leakage = reg_iclamp_lkg[5] * reg_clmp_lkg[4:0];. 100: load k1'accu into leakage for quickly 1st order update. 22h (0644h) iclamp_r_lkg[5:0] 5:0 [5]: sign bit. 0: posetive. 1: negative. [4:0] : magnitude. 0 ~ 31 lsb of +-10ua/32. see reg_iclamp_lkg_mode. reg0645 7: 0 default : 0x08 access : r/w iclamp_r_dlkg_max[5:0] 7:2 delta_leakage is bounded by +- (reg_clmp_dlkg_max / 512). +- 1/8. 22h (0645h) iclamp_r_frez_zero 1 1 : set clmp_dsm = 0 when frez. 0: set clmp_dsm = lkg when frez. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 183 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description iclamp_r_lkg_mode[2] 0 see description of '0644h'. reg0646 7: 0 default : 0x00 access : r/w - 7:2 reserved. iclamp_r_2dsm 1 1 : 2nd-order. 0: 1st-order. 23h (0646h) iclamp_r_frez_dsm 0 1 : delta-sigma frozen. clamp_fpga/chip[5:0] = round{clmp_dsm[15:10]+clmp_dsm[9]}. 0: delta-sigma on. - 7: 0 default : - access : - 23h (0647h) - - reserved. reg064c 7: 0 default : 0x80 access : r/w 26h (064ch) iclamp_g_blank_lvl[7:0] 7:0 blanking level = 128 (rgb). reg064d 7: 0 default : 0x00 access : r/w - 7:4 reserved. 26h (064dh) iclamp_g_blank_lvl[11:8] 3: 0 see description of '064ch'. reg064e 7: 0 default : 0x05 access : r/w 27h (064eh) iclamp_g_lock_level[7:0] 7:0 lock level threshold. reg064f 7: 0 default : 0x00 access : r/w - 7:4 reserved. 27h (064fh) iclamp_g_lock_level[11:8] 3: 0 see description of '064eh'. reg0650 7: 0 default : 0xd0 access : r/w 28h (0650h) iclamp_g_lock_cnt[7:0] 7:0 match reg_iclamp_lock_level counter. reg0651 7: 0 default : 0x07 access : r/w - 7:5 reserved. 28h (0651h) iclamp_g_lock_cnt[12:8] 4: 0 see description of '0650h'. reg0652 7: 0 default : 0x60 access : r/w iclamp_g_k1_stb[0] 7 k1 = 2^(clmp_k1[6:3]-8-2) * (1 + clmp_k1[2:0]/8). for stable. 29h (0652h) iclamp_g_k1_ini[6:0] 6: 0 k1 = 2^(clmp_k1[6:3]-8-2) * (1 + clmp_k1[2:0]/8). for initial. reg0653 7: 0 default : 0x20 access : r/w - 7:6 reserved. 29h (0653h) iclamp_g_k1_stb[6:1] 5: 0 see description of '0652h'. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 184 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description reg0654 7: 0 default : 0xa0 access : r/w iclamp_g_k1_en 7 clamping = leakage + err * gain_true * k1 * k1_en;. 2ah (0654h) iclamp_g_k2[6:0] 6: 0 k2 = 2^(clmp_k2[6:3]-8) * (1 + clmp_k2[2:0]/8);. reg0655 7: 0 default : 0x03 access : r/w - 7:5 reserved. iclamp_g_frez_clmp[2:0] 4:2 clamping = leakage. leakage is frozen. (coast). k1_en = 0 and k2_en = 0. frez_clmp = frez_clmp_1 | frez_clmp_2 | frez_clmp_3;. iclamp_g_type 1 0 : bottom clamping, rgb/ypbpr = 0;. 1: back-porch calmping. 2ah (0655h) iclamp_g_k2_en 0 leakage = leakage + err * gain_true * k1 * k2 * k2_en;. reg0656 7: 0 default : 0x00 access : r/w 2bh (0656h) iclamp_g_agc_fine[7:0] 7:0 agc fine gain. reg0657 7: 0 default : 0x1c access : r/w - 7:6 reserved. iclamp_g_agc_coarse[1:0] 5:4 agc coarse gain. 2bh (0657h) iclamp_g_agc_fine[11:8] 3: 0 see description of '0656h'. reg0658 7: 0 default : 0x40 access : r/w 2ch (0658h) iclamp_g_pga_ofst[7:0] 7:0 pga offset. reg0659 7: 0 default : 0x05 access : r/w - 7:5 reserved. 2ch (0659h) iclamp_g_err_max[4:0] 4:0 bac_porch_level error < +- reg_clmp_err_max <= +-31 * 8 !!!. reg065a 7: 0 default : 0x4a access : r/w 2dh (065ah) iclamp_g_lkg_mode[1:0] 7: 6 001: adaptive leakage tracking. 001: adaptive leakage tracking. leakage is bounded by +- reg_iclamp_lkg[4:0]. 010: freeze leakage. 011: load leakage = reg_iclamp_lkg[5] * reg_clmp_lkg[4:0];. 100: load k1'accu into leakage for quickly 1st order mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 185 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description update. iclamp_g_lkg[5:0] 5:0 [5]: sign bit. 0: posetive. 1: negative. [4:0] : magnitude. 0 ~ 31 lsb of +-10ua/32. see reg_iclamp_lkg_mode. reg065b 7: 0 default : 0x08 access : r/w iclamp_g_dlkg_max[5:0] 7:2 delta_leakage is bounded by +- (reg_clmp_dlkg_max / 512). +- 1/8. iclamp_g_frez_zero 1 1 : set clmp_dsm = 0 when frez. 0: set clmp_dsm = lkg when frez. 2dh (065bh) iclamp_g_lkg_mode[2] 0 see description of '065ah'. reg065c 7: 0 default : 0x00 access : r/w - 7:2 reserved. iclamp_g_2dsm 1 1 : 2nd-order. 0: 1st-order. 2eh (065ch) iclamp_g_frez_dsm 0 1 : delta-sigma frozen. clamp_fpga/chip[5:0] = round{clmp_dsm[15:10]+clmp_dsm[9]}. 0: delta-sigma on. - 7: 0 default : - access : - 2eh (065dh) - - reserved. reg0660 7: 0 default : 0x80 access : r/w 30h (0660h) iclamp_b_blank_lvl[7:0] 7:0 blanking level = 128 (rgb). reg0661 7: 0 default : 0x00 access : r/w - 7:4 reserved. 30h (0661h) iclamp_b_blank_lvl[11:8] 3: 0 see description of '0660h'. reg0662 7: 0 default : 0x05 access : r/w 31h (0662h) iclamp_b_lock_level[7:0] 7:0 lock level threshold. reg0663 7: 0 default : 0x00 access : r/w - 7:4 reserved. 31h (0663h) iclamp_b_lock_level[11:8] 3: 0 see description of '0662h'. 32h reg0664 7: 0 default : 0xd0 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 186 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description (0664h) iclamp_b_lock_cnt[7:0] 7:0 match reg_iclamp_lock_level counter. reg0665 7: 0 default : 0x07 access : r/w - 7:5 reserved. 32h (0665h) iclamp_b_lock_cnt[12:8] 4: 0 see description of '0664h'. reg0666 7: 0 default : 0x60 access : r/w iclamp_b_k1_stb[0] 7 k1 = 2^(clmp_k1[6:3]-8-2) * (1 + clmp_k1[2:0]/8). for stable. 33h (0666h) iclamp_b_k1_ini[6:0] 6: 0 k1 = 2^(clmp_k1[6:3]-8-2) * (1 + clmp_k1[2:0]/8). for initial. reg0667 7: 0 default : 0x20 access : r/w - 7:6 reserved. 33h (0667h) iclamp_b_k1_stb[6:1] 5: 0 see description of '0666h'. reg0668 7: 0 default : 0xa0 access : r/w iclamp_b_k1_en 7 clamping = leakage + err * gain_true * k1 * k1_en;. 34h (0668h) iclamp_b_k2[6:0] 6: 0 k2 = 2^(clmp_k2[6:3]-8) * (1 + clmp_k2[2:0]/8);. reg0669 7: 0 default : 0x03 access : r/w - 7:5 reserved. iclamp_b_frez_clmp[2:0] 4:2 clamping = leakage. leakage is frozen. (coast). k1_en = 0 and k2_en = 0. frez_clmp = frez_clmp_1 | frez_clmp_2 | frez_clmp_3;. iclamp_b_type 1 0 : bottom clamping, rgb/ypbpr = 0;. 1: back-porch calmping. 34h (0669h) iclamp_b_k2_en 0 leakage = leakage + err * gain_true * k1 * k2 * k2_en;. reg066a 7: 0 default : 0x00 access : r/w 35h (066ah) iclamp_b_agc_fine[7:0] 7:0 agc fine gain. reg066b 7: 0 default : 0x1c access : r/w - 7:6 reserved. iclamp_b_agc_coarse[1:0] 5:4 agc coarse gain. 35h (066bh) iclamp_b_agc_fine[11:8] 3: 0 see description of '066ah'. 36h reg066c 7: 0 default : 0x40 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 187 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description (066ch) iclamp_b_pga_ofst[7:0] 7:0 pga offset. reg066d 7: 0 default : 0x05 access : r/w - 7:5 reserved. 36h (066dh) iclamp_b_err_max[4:0] 4:0 bac_porch_level error < +- reg_clmp_err_max <= +-31 * 8 !!!. reg066e 7: 0 default : 0x4a access : r/w iclamp_b_lkg_mode[1:0] 7: 6 001: adaptive leakage tracking. 001: adaptive leakage tracking. leakage is bounded by +- reg_iclamp_lkg[4:0]. 010: freeze leakage. 011: load leakage = reg_iclamp_lkg[5] * reg_clmp_lkg[4:0];. 100: load k1'accu into leakage for quickly 1st order update. 37h (066eh) iclamp_b_lkg[5:0] 5:0 [5]: sign bit. 0: posetive. 1: negative. [4:0] : magnitude. 0 ~ 31 lsb of +-10ua/32. see reg_iclamp_lkg_mode. reg066f 7: 0 default : 0x08 access : r/w iclamp_b_dlkg_max[5:0] 7:2 delta_leakage is bounded by +- (reg_clmp_dlkg_max / 512). +- 1/8. iclamp_b_frez_zero 1 1 : set clmp_dsm = 0 when frez. 0: set clmp_dsm = lkg when frez. 37h (066fh) iclamp_b_lkg_mode[2] 0 see description of '066eh'. reg0670 7: 0 default : 0x00 access : r/w - 7:2 reserved. iclamp_b_2dsm 1 1 : 2nd-order. 0: 1st-order. 38h (0670h) iclamp_b_frez_dsm 0 1 : delta-sigma frozen. clamp_fpga/chip[5:0] = round{clmp_dsm[15:10]+clmp_dsm[9]}. 0: delta-sigma on. 38 h - 7: 0 default : - access : - mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 188 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description (0671h) - - reserved. - 7: 0 default : - access : - 3ah ~ 3fh (0674h ~ 067fh) - - reserved. reg0682 7: 0 default : 0x20 access : r/w 41h (0682h) hact_delay[7:0] 7:0 delay for hsout pulse. reg0683 7: 0 default : 0x00 access : r/w - 7:4 reserved. 41h (0683h) hact_delay[11:8] 3: 0 see description of '0682h'. reg0684 7: 0 default : 0x20 access : r/w 42h (0684h) hact_duration[7:0] 7:0 duration for hact window. reg0685 7: 0 default : 0x00 access : r/w - 7:4 reserved. 42h (0685h) hact_duration[11:8] 3: 0 see description of '0684h'. reg0688 7: 0 default : 0x80 access : r/w 44h (0688h) ug_r_black_level[7:0] 7:0 black level(12). reg0689 7: 0 default : 0x00 access : r/w - 7 reserved. ug_r_pix_sel[2:0] 6:4 pixel select. 44h (0689h) ug_r_black_level[11:8] 3: 0 see description of '0688h'. reg068a 7: 0 default : 0x00 access : r/w 45h (068ah) ug_r_user_gain[7:0] 7: 0 user gain(14.12). reg068b 7: 0 default : 0x10 access : r/w - 7:6 reserved. 45h (068bh) ug_r_user_gain[13:8] 5: 0 see description of '068ah'. reg068c 7: 0 default : 0x00 access : r/w 46h (068ch) ug_r_user_offset[7:0] 7: 0 user offset (s12). reg068d 7: 0 default : 0x00 access : r/w - 7 reserved. ug_r_dit_mode[1:0] 6: 5 00: round, 01:truncate, 10:dithering. 46h (068dh) ug_r_user_offset[12:8] 4: 0 see description of '068ch'. reg068e 7: 0 default : 0x80 access : r/w 47h (068eh) ug_g_black_level[7:0] 7:0 black level(12). mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 189 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description reg068f 7: 0 default : 0x00 access : r/w - 7 reserved. ug_g_pix_sel[2:0] 6:4 pixel select. 47h (068fh) ug_g_black_level[11:8] 3: 0 see description of '068eh'. reg0690 7: 0 default : 0x00 access : r/w 48h (0690h) ug_g_user_gain[7:0] 7: 0 user gain(14.12). reg0691 7: 0 default : 0x10 access : r/w - 7:6 reserved. 48h (0691h) ug_g_user_gain[13:8] 5: 0 see description of '0690h'. reg0692 7: 0 default : 0x00 access : r/w 49h (0692h) ug_g_user_offset[7:0] 7: 0 user offset (s12). reg0693 7: 0 default : 0x00 access : r/w - 7 reserved. ug_g_dit_mode[1:0] 6: 5 00: round, 01:truncate, 10:dithering. 49h (0693h) ug_g_user_offset[12:8] 4: 0 see description of '0692h'. reg0694 7: 0 default : 0x80 access : r/w 4ah (0694h) ug_b_black_level[7:0] 7:0 black level(12). reg0695 7: 0 default : 0x00 access : r/w - 7 reserved. ug_b_pix_sel[2:0] 6:4 pixel select. 4ah (0695h) ug_b_black_level[11:8] 3: 0 see description of '0694h'. reg0696 7: 0 default : 0x00 access : r/w 4bh (0696h) ug_b_user_gain[7:0] 7: 0 user gain(14.12). reg0697 7: 0 default : 0x10 access : r/w - 7:6 reserved. 4bh (0697h) ug_b_user_gain[13:8] 5: 0 see description of '0696h'. reg0698 7: 0 default : 0x00 access : r/w 4ch (0698h) ug_b_user_offset[7:0] 7: 0 user offset (s12). reg0699 7: 0 default : 0x00 access : r/w - 7 reserved. ug_b_dit_mode[1:0] 6: 5 00: round, 01:truncate, 10:dithering. 4ch (0699h) ug_b_user_offset[12:8] 4: 0 see description of '0698h'. 51h reg06a2 7: 0 default : 0x0f access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 190 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description - 7 reserved. ug_rgb_ov 6 override ug_black/ug_gain/ug_offset. (06a2h) ug_rgb_ld_vd_dly[5:0] 5:0 delay for load vd fine gain. reg06a3 7: 0 default : 0x00 access : r/w - 7:3 reserved. 51h (06a3h) ug_rgb_en[2:0] 2:0 enable ug_black/ug_gain/ug_offset register. reg06b4 7: 0 default : 0x44 access : r/w analog_pga_gain_g[3:0] 7:4 adc gain control:. 4'b0000 : 14/5 (vin=0.5vpp). 4'b0001 : 14/5 (vin=0.6vpp). 4'b0010 : 14/5 (vin=0.7vpp). . . 4'b1111 : 14/20 (vin=2.0vpp). 5ah (06b4h) analog_pga_gain_r[3:0] 3:0 adc gain control:. 4'b0000 : 14/5 (vin=0.5vpp). 4'b0001 : 14/5 (vin=0.6vpp). 4'b0010 : 14/5 (vin=0.7vpp). . . 4'b1111 : 14/20 (vin=2.0vpp). reg06b5 7: 0 default : 0x04 access : r/w - 7:4 reserved. 5ah (06b5h) analog_pga_gain_b[3:0] 3:0 adc gain control:. 4'b0000 : 14/5 (vin=0.5vpp). 4'b0001 : 14/5 (vin=0.6vpp). 4'b0010 : 14/5 (vin=0.7vpp). . . 4'b1111 : 14/20 (vin=2.0vpp). reg06b8 7: 0 default : 0x00 access : r/w - 7:3 reserved. fifo_bypass_rgb 2 1 =fifo bypass mode for rgb. 5ch (06b8h) - 1:0 reserved. - 7: 0 default : - access : - 5dh ~ 5dh - - reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 191 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop register (bank = 06) index (absolute) mnemonic bit description (06bah ~ 06bbh) - 7: 0 default : - access : - 60h ~ 63h (06c0h ~ 06c7h) - - reserved. reg06c8 7: 0 default : 0x05 access : r/w 64h (06c8h) mask_delay[7:0] 7:0 delay for hsout/hsync pulse. reg06c9 7: 0 default : 0x00 access : r/w - 7:5 reserved. mask_en 4 enable blank adc for cal. 64h (06c9h) mask_delay[11:8] 3: 0 see description of '06c8h'. reg06ca 7: 0 default : 0x05 access : r/w 65h (06cah) mask_duration[7:0] 7:0 duration for mask window. reg06cb 7: 0 default : 0x00 access : r/w mask_coast 7 1 =enable mask data by coast. mask_cdis 6 1 =disable mask during coast. mask_hsync_or_hsout 5 0 : hsync, 1:hsou. mask_edge 4 se lect mask hsync start edge, 1: hsync rising edge, 0:falling edge. 65h (06cbh) mask_duration[11:8] 3: 0 see description of '06cah'. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 192 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop2 register (bank = 06) adc_dtop2 register (bank = 06) index (absolute) mnemonic bit description reg0602 7:0 default : 0x00 access : r/w adcb_togv2 7 1 =adc b channel interleaving every 2 vsync. adcb_togh2 6 1 =adc g channel interleaving every 2 vsync. adcg_togv2 5 1 =adc r channel interleaving every 2 vsync. adcg_togh2 4 1 =adc b channel interleaving every 2 hsync. adcr_togv2 3 1 =adc g channel interleaving every 2 hsync. adcr_togh2 2 1 =adc r channel interleaving every 2 hsync. rgb_no_vrand 1 1 =no adca interleve v dithering. 01h (0602h) rgb_no_rand 0 1 =no adca interleve h/v dithering. - 7:0 default : - access : - 01h (0603h) - - reserved. reg0604 7:0 default : 0x02 access : r/w - 7:2 reserved. rgb_int_v_polarity 1 1 =adca interleave vsync reference pulse polarity high. 02h (0604h) rgb_int_h_polarity 0 1 =adca interleave hsync reference pulse polarity high. - 7:0 default : - access : - 02h (0605h) - - reserved. reg0606 7:0 default : 0x00 access : r/w 03h (0606h) rgb_self_cal_ref_cyc[7:0] 7:0 adca calibration trigger reference pulse cycle number. reg0607 7:0 default : 0x18 access : r/w, wo - 7:6 reserved. rgb_self_cal_all_gain 5 1 =adca calibration all gain mode enable. rgb_self_cal_mode[1:0] 4:3 [0]=1: adca linear calibration enable. [1]=1: adca offset/gain calibration enable. rgb_self_cal_stop 2 1 =adca calibration stop in live mode. rgb_self_cal_live 1 1 =adca calibration live mode enable. 03h (0607h) rgb_self_cal_start 0 1 =adca calibration start. reg0608 7:0 default : 0x10 access : r/w 04h (0608h) rgb_self_cal_dly[7:0] 7:0 adca claibration delay from reference pulse to mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 193 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop2 register (bank = 06) index (absolute) mnemonic bit description linear/offset/gain calibration state. reg0609 7:0 default : 0x00 access : r/w 04h (0609h) rgb_self_cal_live_wait_dly[7:0] 7:0 adca claibration wait delay number of reference pulse before re-starting new calibration in live mode. reg060a 7:0 default : 0x00 access : r/w - 7:4 reserved. rgb_self_cal_gpuse_sel 3 1 =adca self_cal_g active high during linear calibration & gain calibration;. otherwise, adca self_cal_g active high only during linear calibration. 05h (060ah) rgb_self_cal_bypass[2:0] 2:0 [0]=1: bypass adc r calibration. [1]=1: bypass adc g calibration. [2]=1: bypass adc b calibration. - 7:0 default : - access : - 05h ~ 06h (060bh ~ 060dh) - - reserved. reg060e 7:0 default : 0x00 access : r/w - 7:1 reserved. 07h (060eh) rgb_linear_cal_mode 0 1 =adca linear calibration long mode. reg060f 7:0 default : 0xfe access : r/w rgb_linear_cal_vref_sel[3:0] 7:4 adca vcal setting during linear calibration. 07h (060fh) rgb_linear_cal_pga[3:0] 3:0 adca pga setting during linear calibration. reg0610 7:0 default : 0x00 access : r/w - 7:3 reserved. adcb_lcal_en 2 1 =adc b linear calibration update enable. adcg_lcal_en 1 1 =adc g linear calibration update enable. 08h (0610h) adcr_lcal_en 0 1 =adc r linear calibration update enable. reg0612 7:0 default : 0x1f access : r/w 09h (0612h) rgb_linear_cal_dly[7:0] 7:0 adca linear calibration delay samples after reference pulse rising. reg0613 7:0 default : 0x00 access : r/w - 7:4 reserved. 09h (0613h) rgb_linear_cal_dly[11:8] 3:0 see description of '0612h'. 0ah reg0614 7:0 default : 0xff access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 194 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop2 register (bank = 06) index (absolute) mnemonic bit description (0614h) rgb_linear_cal_dur[7:0] 7:0 adca linear calibration duration samples after reference pulse rising. - 7:0 default : - access : - 0bh ~ 0ch (0616h ~ 0618h) - - reserved. - 7:0 default : - access : - 0dh ~ 12h (061ah ~ 0625h) - - reserved. reg0626 7:0 default : 0x00 access : r/w - 7:4 reserved. adcb_ocal_en 3 1 =adc b offset calibration update enable. adcg_ocal_en 2 1 =adc g offset calibration update enable. adcr_ocal_en 1 1 =adc r offset calibration update enable. 13h (0626h) rgb_offset_cal_mode 0 1 =adca offset calibration long mode. reg0628 7:0 default : 0x1f access : r/w 14h (0628h) rgb_offset_cal_dly[7:0] 7:0 adca offset calibration delay samples after reference pulse rising. reg0629 7:0 default : 0x00 access : r/w - 7:4 reserved. 14h (0629h) rgb_offset_cal_dly[11:8] 3:0 see description of '0628h'. reg062a 7:0 default : 0xff access : r/w 15h (062ah) rgb_offset_cal_dur[7:0] 7:0 adca offset calibration duration samples after reference pulse rising. - 7:0 default : - access : - 16h ~ 18h (062ch ~ 0630h) - - reserved. - 7:0 default : - access : - 19h ~ 1bh (0632h ~ 0636h) - - reserved. - 7:0 default : - access : - 1ch ~ 1eh (0638h ~ 063ch) - - reserved. 1fh reg063e 7:0 default : 0x00 access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 195 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop2 register (bank = 06) index (absolute) mnemonic bit description - 7:5 reserved. rgb_gain_cal_mismatch_onl y 4 1=adca gain calibration only calibrate channel0/channel1 mismatch. adcb_gcal_en 3 1 =adc b gain calibration update enable. adcg_gcal_en 2 1 =adc g gain calibration update enable. adcr_gcal_en 1 1 =adc r gain calibration update enable. (063eh) rgb_gain_cal_mode 0 1 =adca gain calibration long mode. reg0640 7:0 default : 0x1f access : r/w 20h (0640h) rgb_gain_cal_dly[7:0] 7:0 adca gain calibration delay samples after reference pulse rising. reg0641 7:0 default : 0x00 access : r/w - 7:4 reserved. 20h (0641h) rgb_gain_cal_dly[11:8] 3:0 see description of '0640h'. reg0642 7:0 default : 0xff access : r/w 21h (0642h) rgb_gain_cal_dur[7:0] 7:0 adca gain calibration duration samples after reference pulse rising. reg0643 7:0 default : 0xff access : r/w 21h (0643h) rgb_gain_cal_dur[15:8] 7:0 see description of '0642h'. - 7:0 default : - access : - 22h ~ 25h (0644h ~ 064ah) - - reserved. - 7:0 default : - access : - 26h ~ 29h (064ch ~ 0652h) - - reserved. - 7:0 default : - access : - 2ah ~ 2dh (0654h ~ 065ah) - - reserved. reg067e 7:0 default : 0x00 access : r/w rgb_gain_cal_lvref[3:0] 7:4 adca gain calibration low vcal write value. 3fh (067eh) rgb_gain_cal_hvref[3:0] 3:0 adca gain calibration high vcal write value. reg067f 7:0 default : 0x00 access : r/w, wo rgb_gain_cal_vref_wp 7 adca gain calibration vcal write enable. 3fh (067fh) - 6:4 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 196 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop2 register (bank = 06) index (absolute) mnemonic bit description rgb_gain_cal_vref_wg[3:0] 3:0 adca gain calibration vcal write related gain setting. reg0680 7:0 default : 0x00 access : r/w 40h (0680h) rgb_gain_cal_target[7:0] 7:0 adca gain calibration vcal_high-vcal_low target digital code write value. reg0681 7:0 default : 0x00 access : r/w - 7:4 reserved. 40h (0681h) rgb_gain_cal_target[11:8] 3:0 see description of '0680h'. reg0682 7:0 default : 0x00 access : r/w, wo rgb_gain_cal_target_wp 7 adca gain calibration (vcal_high-vcal_low) target digital code write enable. - 6:4 reserved. 41h (0682h) rgb_gain_cal_target_wg[3:0] 3:0 adca gain calibration vcal_high-vcal_low target digital code write related gain setting. - 7:0 default : - access : - 42h ~ 43h (0684h ~ 0687h) - - reserved. - 7:0 default : - access : - 45h ~ 4dh (068ah ~ 069bh) - - reserved. reg06f6 7:0 default : 0x00 access : r/w 7bh (06f6h) rgb_self_cal_ref_dly[7:0] 7:0 the delay samples of adca calibration reference pulse after hsync/vsync. reg06f7 7:0 default : 0x00 access : r/w rgb_self_cal_ref_sel[2:0] 7:5 [2:0]=1xx : adca using vsync as calibration reference pulse. [2:0]=01x : adca using hsync as calibration reference pulse. [2:0]=001 : adca using hsout as calibration reference pulse. [2:0]=000 : adca calibration reference always high. rgb_self_cal_ref_edge 4 1 =adca calibration reference using trailing edge of hsync/vsync. 7bh (06f7h) rgb_self_cal_ref_dly[11:8] 3:0 see description of '06f6h'. 7dh ~ 7fh - 7:0 default : - access : - mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 197 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. adc_dtop2 register (bank = 06) index (absolute) mnemonic bit description (06fah ~ 06ffh) - - reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 198 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) chiptop register (bank = 07) index (absolute) mnemonic bit description reg0702 7:0 default : 0x00 access : r/w sar_ch2_lob_lsb2[1:0] 7:6 the lsb 2-bit of voltage lower bound in mcu sleep mode for channel 2 keypad wakeup. sar_ch2_upb_lsb2[1:0] 5:4 the lsb 2-bit of voltage upper bound in mcu sleep mode for channel 2 keypad wakeup. sar_ch1_lob_lsb2[1:0] 3:2 the lsb 2-bit of voltage lower bound in mcu sleep mode for channel 1 keypad wakeup. 01h (0702h) sar_ch1_upb_lsb2[1:0] 1:0 the lsb 2-bit of voltage upper bound in mcu sleep mode for channel 1 keypad wakeup. reg0703 7:0 default : 0x00 access : r/w - 7:4 reserved. sar_ch3_lob_lsb2[1:0] 3:2 the lsb 2-bit of voltage lower bound in mcu sleep mode for channel 3 keypad wakeup. 01h (0703h) sar_ch3_upb_lsb2[1:0] 1:0 the lsb 2-bit of voltage upper bound in mcu sleep mode for channel 3 keypad wakeup. reg0704 7:0 default : 0x00 access : r/w - 7:5 reserved. 02h (0704h) sar_divctrl[4:0] 4:0 sar operation clock divider selection. reg0705 7:0 default : 0x00 access : r/w - 7 reserved. por_deglitch[2:0] 6:4 for por deglitch setting. - 3:1 reserved. 02h (0705h) sar_oneshot 0 one-shot for sar one-shot mode. reg0706 7:0 default : 0x00 access : r/w - 7:4 reserved. cp1_n_drv[1:0] 3:2 driving control for pad_cp1_n. 03h (0706h) cp1_p_drv[1:0] 1:0 driving control for pad_cp1_p. reg0707 7:0 default : 0x0b access : r/w test_9to12_en 7 se cond test enable bit for test_bus[9:12]. (both of testmode enable and this enable are set, then just can enable test_bus[9:12]). bt656_out_en 6 bt656 out enable bit. 03h (0707h) - 5 reserved. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 199 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description pwm1d_sel 4 pad_pwm1d output select:. 0: normal pwm1d output. 1: cabc output. cp_div_cntr[3:0] 3:0 cp1_p/n frequency divide counter. freq = xin_freq / (cp_div_cntr+1). reg0708 7:0 default : 0xff access : r/w 04h (0708h) new_gpio_en[7:0] 7:0 gpio enable for each new gpio. [0]: pad_clkin. [1]: pad_vd0. [2]: pad_vd1. [3]: pad_vd2. [4]: pad_vd3. [5]: pad_vd4. [6]: pad_vd5. [7]: pad_vd6. [8]: pad_vd7. [9]: pad_int. [10]: pad_pwm1d. [11]: pad_pwm2d. [12]: pad_rout0. [13]: pad_gout4. [14]: pad_clko. [15]: pad_deo. reg0709 7:0 default : 0xff access : r/w 04h (0709h) new_gpio_en[15:8] 7:0 see description of '0708h'. reg070a 7:0 default : 0xff access : r/w 05h (070ah) new_gpio_en[23:16] 7:0 see description of '0708h'. reg070b 7:0 default : 0xff access : r/w 05h (070bh) new_gpio_en[31:24] 7:0 see description of '0708h'. reg070c 7:0 default : 0xff access : r/w 06h (070ch) new_gpio_en[39:32] 7:0 see description of '0708h'. reg070d 7:0 default : 0xff access : r/w 06h (070dh) new_gpio_en[47:40] 7:0 see description of '0708h'. reg070e 7:0 default : 0xff access : r/w 07h (070eh) new_gpio_en[55:48] 7:0 see description of '0708h'. 07h reg070f 7:0 default : 0xff access : r/w mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 200 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description (070fh) new_gpio_en[63:56] 7:0 see description of '0708h'. reg0710 7:0 default : 0x00 access : r/w 08h (0710h) new_gpio_o[7:0] 7:0 the value of gpio output for each new gpio. reg0711 7:0 default : 0x00 access : r/w 08h (0711h) new_gpio_o[15:8] 7:0 see description of '0710h'. reg0712 7:0 default : 0x00 access : r/w 09h (0712h) new_gpio_o[23:16] 7:0 see description of '0710h'. reg0713 7:0 default : 0x00 access : r/w 09h (0713h) new_gpio_o[31:24] 7:0 see description of '0710h'. reg0714 7:0 default : 0x00 access : r/w 0ah (0714h) new_gpio_o[39:32] 7:0 see description of '0710h'. reg0715 7:0 default : 0x00 access : r/w 0ah (0715h) new_gpio_o[47:40] 7:0 see description of '0710h'. reg0716 7:0 default : 0x00 access : r/w 0bh (0716h) new_gpio_o[55:48] 7:0 see description of '0710h'. reg0717 7:0 default : 0x00 access : r/w 0bh (0717h) new_gpio_o[63:56] 7:0 see description of '0710h'. reg0718 7:0 default : 0xff access : r/w 0ch (0718h) new_gpio_oen[7:0] 7:0 the value of gpio output enable for each new gpio. 0: gpio as output. 1: gpio as input. reg0719 7:0 default : 0xff access : r/w 0ch (0719h) new_gpio_oen[15:8] 7:0 see description of '0718h'. reg071a 7:0 default : 0xff access : r/w 0dh (071ah) new_gpio_oen[23:16] 7:0 see description of '0718h'. reg071b 7:0 default : 0xff access : r/w 0dh (071bh) new_gpio_oen[31:24] 7:0 see description of '0718h'. reg071c 7:0 default : 0xff access : r/w 0eh (071ch) new_gpio_oen[39:32] 7:0 see description of '0718h'. reg071d 7:0 default : 0xff access : r/w 0eh (071dh) new_gpio_oen[47:40] 7:0 see description of '0718h'. reg071e 7:0 default : 0xff access : r/w 0fh (071eh) new_gpio_oen[55:48] 7:0 see description of '0718h'. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 201 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description reg071f 7:0 default : 0xff access : r/w 0fh (071fh) new_gpio_oen[63:56] 7:0 see description of '0718h'. reg0720 7:0 default : 0x00 access : ro 10h (0720h) new_gpio_i[7:0] 7:0 the read value of for each new gpio. reg0721 7:0 default : 0x00 access : ro 10h (0721h) new_gpio_i[15:8] 7:0 see description of '0720h'. reg0722 7:0 default : 0x00 access : ro 11h (0722h) new_gpio_i[23:16] 7:0 see description of '0720h'. reg0723 7:0 default : 0x00 access : ro 11h (0723h) new_gpio_i[31:24] 7:0 see description of '0720h'. reg0724 7:0 default : 0x00 access : ro 12h (0724h) new_gpio_i[39:32] 7:0 see description of '0720h'. reg0725 7:0 default : 0x00 access : ro 12h (0725h) new_gpio_i[47:40] 7:0 see description of '0720h'. reg0726 7:0 default : 0x00 access : ro 13h (0726h) new_gpio_i[55:48] 7:0 see description of '0720h'. reg0727 7:0 default : 0x00 access : ro 13h (0727h) new_gpio_i[63:56] 7:0 see description of '0720h'. reg0728 7:0 default : 0x00 access : ro 14h (0728h) test_24bit_bus_status[7:0] 7:0 the read value of test 24bit bus. reg0729 7:0 default : 0x00 access : ro 14h (0729h) test_24bit_bus_status[15:8] 7:0 see description of '0728h'. reg072a 7:0 default : 0x00 access : ro 15h (072ah) test_24bit_bus_status[23:16] 7:0 see description of '0728h'. reg0740 7:0 default : 0x00 access : r/w - 7:5 reserved. bt656_out_clk_gate 4 0 : enable bt656 out clock. 1: disable bt656 out clock. pwm_out_clk_gate 3 0 : enable pwm out clock. 1: disable pwm out clock. mod_cal_clk_gate 2 0 : enable mod cal clock. 1: disable mod cal clock. 20h (0740h) fscclk_div4_gate 1 0 : enable mvd digital front-end divide 4 clock. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 202 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description 1: disable mvd digital front-end divide 4 clock. fscclk_div2_gate 0 0 : enable mvd digital front-end divide 2 clock. 1: disable mvd digital front-end divide 2 clock. reg0742 7:0 default : 0x00 access : r/w - 7:5 reserved. bt656_out_clk_inv 4 bt656 out clock inverting. pwm_out_clk_inv 3 pwm out clock inverting. mod_cal_clk_inv 2 mod cal clock inverting. fscclk_div4_inv 1 mvd digital front-end divide 4 clock inverting. 21h (0742h) fscclk_div2_inv 0 mvd digital front-end divide 2 clock inverting. reg0744 7:0 default : 0x21 access : r/w mod_cal_clk_sel[1:0] 7:6 mod cal clock selection. 0: xin/8. 1: xin/16. 2: xin/32. 3: dft clock. fscclk_sel[1:0] 5:4 mvd digital front-end clock selection. 0: fscclk/4. 1: fscclk/2. 2: fscclk. 3: dft clock. fscclk_div4_sel[1:0] 3:2 mvd digital front-end divide 4 clock selection. 0: fscclk/4. 1: fscclk/2. 2: fscclk. 3: dft clock. 22h (0744h) fscclk_div2_sel[1:0] 1:0 mvd digital front-end divide 2 clock selection. 0: fscclk/4. 1: fscclk/2. 2: fscclk. 3: dft clock. reg0745 7:0 default : 0x60 access : r/w 22h (0745h) bt656_out_clk_sel[1:0] 7:6 odclk selection. 0: idclk. 1: lpll/2. 2: lpll. 3: dft clock. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 203 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description odgen_clk_sel[1:0] 5:4 odclk selection. 0: idclk. 1: lpll/2. 2: lpll. 3: dft clock. clk_atop_sel[1:0] 3:2 mod cal clock selection. 0: 432mhz. 1: null. 2: 216mhz. 3: dft clock. pwm_out_clk_sel[1:0] 1:0 mod cal clock selection. 0: odclk. 1: odclk/2. 2: dft clock. 3: dft clock. - 7:0 default : - access : - 30h ~ 33h (0760h ~ 0767h) - - reserved. reg0780 7:0 default : 0xff access : r/w 40h (0780h) v_blk_st1_vpos[7:0] 7:0 bt656 v blanking 1st start v position. reg0781 7:0 default : 0x0f access : r/w - 7:4 reserved. 40h (0781h) v_blk_st1_vpos[11:8] 3:0 see description of '0780h'. reg0782 7:0 default : 0xff access : r/w 41h (0782h) v_blk_st1_hpos[7:0] 7:0 bt656 v blanking 1st start h position. reg0783 7:0 default : 0x0f access : r/w - 7:4 reserved. 41h (0783h) v_blk_st1_hpos[11:8] 3:0 see description of '0782h'. reg0784 7:0 default : 0xff access : r/w 42h (0784h) v_blk_end1_vpos[7:0] 7:0 bt656 v blanking 1st endt v position. reg0785 7:0 default : 0x0f access : r/w - 7:4 reserved. 42h (0785h) v_blk_end1_vpos[11:8] 3:0 see description of '0784h'. reg0786 7:0 default : 0xff access : r/w 43h (0786h) v_blk_end1_hpos[7:0] 7:0 bt656 v blanking 1st end h position. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 204 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description reg0787 7:0 default : 0x0f access : r/w - 7:4 reserved. 43h (0787h) v_blk_end1_hpos[11:8] 3:0 see description of '0786h'. reg0788 7:0 default : 0xff access : r/w 44h (0788h) v_blk_st2_vpos[7:0] 7:0 bt656 v blanking 2nd start v position. reg0789 7:0 default : 0x0f access : r/w - 7:4 reserved. 44h (0789h) v_blk_st2_vpos[11:8] 3:0 see description of '0788h'. reg078a 7:0 default : 0xff access : r/w 45h (078ah) v_blk_st2_hpos[7:0] 7:0 bt656 v blanking 2nd start h position. reg078b 7:0 default : 0x0f access : r/w - 7:4 reserved. 45h (078bh) v_blk_st2_hpos[11:8] 3:0 see description of '078ah'. reg078c 7:0 default : 0xff access : r/w 46h (078ch) v_blk_end2_vpos[7:0] 7:0 bt656 v blanking 2nd endt v position. reg078d 7:0 default : 0x0f access : r/w - 7:4 reserved. 46h (078dh) v_blk_end2_vpos[11:8] 3:0 see description of '078ch'. reg078e 7:0 default : 0xff access : r/w 47h (078eh) v_blk_end2_hpos[7:0] 7:0 bt656 v blanking 2nd end h position. reg078f 7:0 default : 0x0f access : r/w - 7:4 reserved. 47h (078fh) v_blk_end2_hpos[11:8] 3:0 see description of '078eh'. reg0790 7:0 default : 0xff access : r/w 48h (0790h) fld_st1_vpos[7:0] 7:0 bt656 field1 start v position. reg0791 7:0 default : 0x0f access : r/w - 7:4 reserved. 48h (0791h) fld_st1_vpos[11:8] 3:0 see description of '0790h'. reg0792 7:0 default : 0xff access : r/w 49h (0792h) fld_st1_hpos[7:0] 7:0 bt656 field1 start h position. reg0793 7:0 default : 0x0f access : r/w - 7:4 reserved. 49h (0793h) fld_st1_hpos[11:8] 3:0 see description of '0792h'. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 205 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. chiptop register (bank = 07) index (absolute) mnemonic bit description reg0794 7:0 default : 0xff access : r/w 4ah (0794h) fld_st2_vpos[7:0] 7:0 bt656 field2 start v position. reg0795 7:0 default : 0x0f access : r/w - 7:4 reserved. 4ah (0795h) fld_st2_vpos[11:8] 3:0 see description of '0794h'. reg0796 7:0 default : 0xff access : r/w 4bh (0796h) fld_st2_hpos[7:0] 7:0 bt656 field2 start h position. reg0797 7:0 default : 0x0f access : r/w - 7:4 reserved. 4bh (0797h) fld_st2_hpos[11:8] 3:0 see description of '0796h'. reg0798 7:0 default : 0x00 access : r/w 4ch (0798h) mask_y_blk_va[7:0] 7:0 bt656 mask y blk value. reg0799 7:0 default : 0x08 access : r/w - 7 reserved. bt656_8bit 6 bt656 8bit mode. ddr_hl_swap 5 bt656 ddr high low swap. crcb_swap 4 s wap crcb position in 422. 444_bypass 3 enable 444 to 422 conversion. mask_y_blk_en 2 bt656 mask y blk enable. 4ch (0799h) mask_y_blk_va[9:8] 1:0 see description of '0798h'. reg079a 7:0 default : 0x00 access : r/w 4dh (079ah) mask_c_blk_va[7:0] 7:0 bt656 mask c blk value. reg079b 7:0 default : 0x00 access : r/w - 7:3 reserved. mask_c_blk_en 2 bt656 mask c blk enable. 4dh (079bh) mask_c_blk_va[9:8] 1:0 see description of '079ah'. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 206 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. register table revision history date bank register 10/28/ 10 created first version. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/
MST705 small size lcd tv processor with video decoder preliminary data sheet version 0.1 - 207 - 11/2/2010 copyright ? 2010 mstar semiconductor, inc. all rights reserved. this page is intended to be left blank. mstar confidential for m? w3^l_t/y?b?g ?pqls? internal use only free datasheet http://www..net/

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